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| rev. 3 june 2005 1/172 st72260gx, st72262gx, st72264gx 8-bit mcu with flash or rom memory, adc, two 16-bit timers, i 2 c, spi, sci interfaces memories ? 4 k or 8 kbytes program memory: rom or single voltage extended flash (xflash) with read-out protection write protection and in- circuit programming and in-application pro- gramming (icp and iap). 10k write/erase cy- cles guaranteed, data retention: 20 years at 55c. ? 256 bytes ram clock, reset and supply management ? enhanced reset system ? enhanced low voltage supply supervisor (lvd) with 3 programmable levels and auxil- iary voltage detector (avd) with interrupt ca- pability for implementing safe power-down procedures ? clock sources: crystal/ceramic resonator os- cillators, internal rc oscillator and bypass for external clock ? pll for 2x frequency multiplication ? clock-out capability ? 4 power saving modes: halt, active halt,wait and slow interrupt management ? nested interrupt controller ? 10 interrupt vectors plus trap and reset ? 22 external interrupt lines (on 2 vectors) 22 i/o ports ? 22 multifunctional bi directional i/o lines ? 20 alternate function lines ? 8 high sink outputs 4 timers ? main clock controller with real time base and clock-out capabilities ? configurable watchdog timer ? two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- er, pwm and pulse generator modes 3 communication interfaces ? spi synchronous serial interface ?i 2 c multimaster interfac e (smbus v1.1 com- pliant) ? sci asynchronous serial interface 1 analog peripheral ? 10-bit adc with 6 input channels instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode de- tection ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction development tools ? full hardware/software development package device summary sdip32 so28 lfbga 6x6mm features st72260g1 st72262g1 st72262g2 st72264g1 st72264g2 program memory - bytes 4k 4k 8k 4k 8k ram (stack) - bytes 256 (128) peripherals watchdog timer, rtc, two16-bit timers, spi watchdog timer, rtc, two 16-bit timers, spi, adc watchdog timer, rtc, two 16-bit timers, spi, sci, i 2 c, adc operating supply 2.7 v to 5.5 v cpu frequency up to 8 mhz (with oscillator up to 16 mhz) pll 4/8 mhz operating temperature -40 c to +85 c -40 c to +85 c 0 c to +70 c / -40 c to +85 c packages so28 / sdip32 so28 / sdip32 lfbga 1
table of contents 172 2/172 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.4 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 9.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.7 device-specific i/o port configur ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.8 i/o port register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2 table of contents 3/172 10.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 i/o port alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.3 miscellaneous register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 main clock controller with real time clock (mcc/rtc) . . . . . . . . . . . . . 53 11.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.5 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.6 i2c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.7 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 153 13.12 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3 lead-free package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 162 15.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 62 15.2 device ordering info rmation and transfer of customer code . . . . 164 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.1 all flash and rom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.2 flash devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 3 st72260gx, st72262gx, st72264gx 4/172 to obtain the most recent version of this datasheet, please check at www.st.com>produc ts>technical literature>datasheet please note that the list of known limitations can be found at the end of this document on page 168 . st72260gx, st72262gx, st72264gx 5/172 1 introduction the st72260gx, st72262gx and st72264gx devices are members of the st7 microcontroller family. they can be grouped as follows : ? st72264gx devices are designed for mid-range applications with adc, i 2 c and sci interface ca- pabilities. ? st72262gx devices target the same range of applications but without i 2 c interface or sci. ? st72260gx devices are for applications that do not need adc, i 2 c peripherals or sci. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. the st72f260g, st72f262g, and st72f264g versions feature single-voltage flash memory with byte-by-byte in-circuit programming (icp) capabilities. under software control, all devices can be placed in wait, slow, active-halt or halt mode, re- ducing power consumption when the application is in idle or stand-by state. the enhanced instruction set and addressing modes of the st7 offer bo th power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. for easy reference, all pa rametric data is located in section 13 on page 126 . related documentation an1365: guidelines for migrating st72c254 ap- plications to st72f264 figure 1. general block diagram 8-bit core alu address and data bus osc1 osc2 reset port b 16-bit timer a port a spi port c 10-bit adc* pb7:0 (8 bits) pc5:0 (6 bits) multi osc internal clock control ram (256 bytes) pa7:0 (8 bits) v ss v dd power supply 16-bit timer b program (4 or 8k bytes) lvd sci* memory icd watchdog i 2 c* *not available on some devices, see device summary on page 1. mcc/rtc st72260gx, st72262gx, st72264gx 6/172 2 pin description figure 2. 28-pin so package pinout figure 3. 32-pin sdip package pinout 15 16 17 18 19 20 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reset osc1 ain3 2 /icap2_b/pc3 ain4 2 /ocmp2_b/pc4 ain5/extclk_a/pc5 icap1_a/pb0 ocmp1_a/pb1 icap2_a/pb2 ocmp2_a/pb3 mosi/pb4 miso/pb5 sck/pb6 ss /pb7 osc2 v dd v ss pc2/mco/ain2 2 pc1/ocmp1_b/ain1 2 pc0/icap1_b/ain0 2 pa7 (hs)/tdo 3 pa6 (hs)/sdai 3 pa5(hs)/rdi 3 pa4 (hs)/scli 3 pa3 (hs) pa2 (hs) pa1 (hs)/iccdata pa0 (hs)/iccclk iccsel ei1 ei0 ei0 or ei1 1 (hs) 20ma high sink capability eix associated external interrupt vector 1 configurable by option byte 2 alternate function not available on st72260 3 alternate function not available on st72260 and st72262 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 reset osc1 ain3 2 /icap2_b/pc3 ain4 2 /ocmp2_b/pc4 ain5 2 /extclk_a/pc5 icap1_a/pb0 ocmp1_a/pb1 icap2_a/pb2 ocmp2_a/pb3 mosi/pb4 miso/pb5 sck/pb6 ss /pb7 osc2 nc nc v dd v ss pc2/mco/ain2 2 pc1/ocmp1_b/ain1 2 pc0/icap1_b/ain0 2 pa7 (hs)/tdo 3 pa6 (hsi/sdai 3 pa5 (hs)/rdi 3 pa4 (hs)/scli 3 pa3 (hs) pa2 (hs) pa1 (hs)/iccdata pa0 (hs)/iccclk iccsel nc nc ei1 ei0 ei0 ei1 ei0 or ei1 1 (hs) 20ma high sink capability eix associated external interrupt vector 1 configurable by option byte 2 alternate function not available on st72260 3 alternate function not available on st72260 and st72262 st72260gx, st72262gx, st72264gx 7/172 pin description (cont?d) figure 4. tfbga package pinout (view through package) a b c d e f 123456 st72260gx, st72262gx, st72264gx 8/172 pin description (cont?d) for external pin connection guidelines, refer to section 13 "electrical characteristics" on page 126 . legend / abbreviations for table 1 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c t = cmos 0.3 v dd /0.7 v dd with input trigger output level: hs = 20 ma high sink (on n-buffer only) port and control configuration: ? input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog ? output: od = open drain 2) , pp = push-pull refer to section 9 "i/o ports" on page 38 for more details on the software configuration of the i/o ports. the reset configuration of ea ch pin is shown in bold. th is configuration is valid as long as the device is in reset state. table 1. device pin description pin n pin name type level port / control main function (after reset) alternate function sdip32 so28 bga input output input output float wpu int ana od pp 1 1 a3 reset i/o c t xx top priority non maskable interrupt (ac- tive low) 2 2 c4 osc1 3) i external clock input or resonator oscilla- tor inverter input or resistor input for rc oscillator 3 3 b3 osc2 3) o resonator oscillator inverter output or ca- pacitor input for rc oscillator 4 4 a2 pb7/ss i/o c t x ei1 x x port b7 spi slave select (active low) 5 5 a1 pb6/sck i/o c t x ei1 x x port b6 spi serial clock 6 6 b1 pb5/miso i/o c t x ei1 x x port b5 spi master in/ slave out data 7 7 b2 pb4/mosi i/o c t x ei1 x x port b4 spi master out / slave in data 8 c1 nc not connected 9 c2 nc d1 nc 10 8 c3 pb3/ocmp2_a i/o c t x ei1 x x port b3 timer a output compare 2 11 9 d2 pb2/icap2_a i/o c t x ei1 x x port b2 timer a input capture 2 12 10 e1 pb1 /ocmp1_a i/o c t x ei1 x x port b1 timer a output compare 1 caution: negative current injection not allowed on this pin 4) . 13 11 f1 pb0 /icap1_a i/o c t x ei1 x x port b0 timer a input capture 1 caution: negative current injection not allowed on this pin 4) . 14 12 f2 pc5/extclk_a/ain5 i/o c t x ei0/ei1 x x x port c5 timer a input clock or adc analog input 5 st72260gx, st72262gx, st72264gx 9/172 notes : 1. in the interrupt input column, ?eix? defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is a pull-up interrupt in- put, otherwise the configuration is a floating interrupt i nput. port c is mapped to ei0 or ei1 by option byte. 2. in the open drain output column, ?t? defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). see section 9 "i/o ports" on page 38 for more details. 3. osc1 and osc2 pins connect a crystal or ceramic resonator, or an external source to the on-chip os- cillator see section 2 "pin description" on page 6 and section 6.2 "multi-o scillator (mo)" on page 21 for more details. 4: for details refer to section 13.8 on page 144 15 13 e2 pc4/ocmp2_b/ain4 i/o c t x ei0/ei1 x x x port c4 timer b output compare 2 or adc analog input 4 16 14 f3 pc3/ icap2_b/ain3 i/o c t x ei0/ei1 x x x port c3 timer b input capture 2 or adc analog input 3 17 15 e3 pc2/mco/ain2 i/o c t x ei0/ei1 x x x port c2 main clock output (f cpu ) or adc analog input 2 18 16 f4 pc1/ocmp1_b/ain1 i/o c t x ei0/ei1 x x x port c1 timer b output compare 1 or adc analog input 1 19 17 d3 pc0/icap1_b/ain0 i/o c t x ei0/ei1 x x x port c0 timer b input capture 1 or adc analog input 0 20 18 e4 pa7/tdo i/o c t hs x ei0 x x port a7 sci output 21 19 f5 pa6/sdai i/o c t hs x ei0 t port a6 i 2 c data 22 20 f6 pa5 /rdi i/o c t hs x ei0 x x port a5 sci input 23 21 e6 pa4/scli i/o c t hs x ei0 t port a4 i 2 c clock 24 e5 nc not connected 25 d6 nc d5 nc 26 22 c6 pa3 i/o c t hs x ei0 x x port a3 27 23 d4 pa2 i/o c t hs x ei0 x x port a2 c5 nc not connected b6 nc 28 24 a6 pa1/iccdata i/o c t hs x ei0 x x port a1 in circuit communication data 29 25 a5 pa0/iccclk i/o c t hs x ei0 x x port a0 in circuit communication clock 30 26 b5 iccsel i c t x icc mode pin, must be tied low 31 27 a4 v ss s ground 32 28 b4 v dd s main power supply pin n pin name type level port / control main function (after reset) alternate function sdip32 so28 bga input output input output float wpu int ana od pp st72260gx, st72262gx, st72264gx 10/172 3 register & memory map as shown in figure 5 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register location, 256 bytes of ram and up to 8 kbytes of user program memory. the ram space includes up to 128 bytes for the stack from 0100h to 017fh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see fig- ure 5 ) mapped in the upper part of the st7 ad- dressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). the size of flash sector 0 and other device op- tions are configurable by option byte (refer to sec- tion 15.1 on page 162 ). important: memory locations marked as ?re- served? must never be accessed. accessing a re- seved area can have unpredictable effects on the device. related documentation an 985: executing code in st7 ram figure 5. memory map 0000h program memory (4k, 8 kbytes) interrupt & reset vectors hw registers 0080h 007fh (see table 2 ) e000h ffdfh ffe0h ffffh (see table 5 on page 32 ) 0180h reserved 017fh short addressing ram 0100h 017fh 0080h 00ffh ram zero page (128 bytes) stack or 16-bit addressing ram (128 bytes) 4 kbytes 4 kbytes sector 1 sector 0 8k flash ffffh f000h efffh e000h program memory dfffh (256 bytes) st72260gx, st72262gx, st72264gx 11/172 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port c pcdr pcddr pcor port c data register port c data direction register port c option register xx000000h 1) 00h 00h r/w 2) r/w 2) r/w 2) 0003h reserved (1 byte) 0004h 0005h 0006h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w. 0007h reserved (1 byte) 0008h 0009h 000ah port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 00h r/w r/w r/w 000bh to 001bh reserved (17 bytes) 001ch 001dh 001eh 001fh itc ispr0 ispr1 ispr2 ispr3 interrupt software priority register0 interrupt software priority register1 interrupt software priority register2 interrupt software priority register3 ffh ffh ffh ffh r/w r/w r/w r/w 0020h miscr1 miscellanous register 1 00h r/w 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi status register xxh 0xh 00h r/w r/w r/w 0024h watchdog wdgcr watchdog control register 7fh r/w 0025h sicsr system integrity contro l / status register 000x 000x r/w 0026h mcc mccsr main clock contro l / status register 00h r/w 0027h reserved (1 byte) 0028h 0029h 002ah 002bh 002ch 002dh 002eh i 2 c i2ccr i2csr1 i2csr2 i2cccr i2coar1 i2coar2 i2cdr i 2 c control register i 2 c status register 1 i 2 c status register 2 i 2 c clock control register i 2 c own address register 1 i 2 c own address register2 i 2 c data register 00h 00h 00h 00h 00h 40h 00h r/w read only read only r/w r/w r/w r/w 002fh 0030h reserved (2 bytes) st72260gx, st72262gx, st72264gx 12/172 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tascsr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate c ounter high register timer a alternate c ounter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h miscr2 miscellanous register 2 00h r/w 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbscsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b control/status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate c ounter high register timer b alternate c ounter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register1 sci control register2 sci extended receive prescaler register sci extended transmit prescaler register c0h xxh 00h x000 0000h 00h 00h 00h read only r/w r/w r/w r/w r/w r/w 0057h to 006eh reserved (24 bytes) 006fh 0070h 0071h adc adcdrl adcdrh adccsr data register low 3) data register high 3) control/status register 00h 00h 00h read only read only r/w 0072h flash fcsr flash control register 00h r/w 0073h to 007fh reserved (13 bytes) address block register label register name reset status remarks st72260gx, st72262gx, st72264gx 13/172 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 3. for compatibility with the st72c 254, the adcdrl and adcdrh data registers are located with the lsb on the lower address (6fh) and the msb on the higher address (70h). as this scheme is not little en- dian, the adc data registers cannot be treated by c programs as an integer, but have to be treated as two char registers. st72260gx, st72262gx, st72264gx 14/172 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on-board using in-circuit programming or in-application program- ming. the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte read-out and write protection against piracy 4.3 programming modes the st7 can be programmed in three different ways: ? insertion in a programming tool. in this mode, flash sectors 0 and 1 and option byte row can be programmed or erased. ? in-circuit programming. in this mode, flash sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. ? in-application programming. in this mode, sector 1 can be programmed or erased with- out removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit commu- nication) which allows an st7 plugged on a print- ed circuit board (pcb) to communicate with an ex- ternal programming device connected via cable. icp is performed in three steps: switch the st7 to icc mode (in-circuit communi- cations). this is done by driving a specific signal sequence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory contain- ing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. ? download icp driver code in ram from the iccdata pin ? execute icp driver code in ram to program the flash memory depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in application programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully contro lled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) iap mode can be used to program any memory ar- eas except sector 0, which is write/erase protect- ed to allow recovery in case errors occur during the programming operation. st72260gx, st72262gx, st72264gx 15/172 flash program memory (cont?d) 4.4 icc interface icp needs a minimum of 4 and up to 7 pins to be connected to the programming tool. these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input serial data pin ? iccsel: icc selection (n ot required on devic- es without iccsel pin) ? osc1: main clock input for external source (not required on devices without osc1/osc2 pins) ?v dd : application board power supply (option- al, see note 3) notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor val- ues. 2. during the icp session, the programming tool must control the reset pin. this can lead to con- flicts between the programming tool and the appli- cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli- cation reset circuit in this case. when using a classical rc network with r>1k or a reset man- agement ic with open drain output and pull-up re- sistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program- ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 pin of the st7 when the clock is not available in the ap- plication or if the selected clock option is not pro- grammed in the option byte. st7 devices with mul- ti-oscillator capability ne ed to have osc2 ground- ed in this case. figure 6. typical icc interface icc connector iccdata iccclk reset vdd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10k ? vss iccsel st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4) st72260gx, st72262gx, st72264gx 16/172 flash program memory (cont?d) 4.5 memory protection there are two different types of memory protec- tion: read out protection and write/erase protec- tion which can be applied individually. 4.5.1 read out protection read-out protection, when selected, provides a protection against program memory content ex- traction and against write access to flash memo- ry. even if no protection can be considered as to- tally unbreakable, the feature provides a very high level of protection for a general purpose microcon- troller. in flash devices, this protection is removed by re- programming the option. in this case the program memory is automatically erased and the device can be reprogrammed. read-out protection selection depends on the de- vice type: ? in flash devices it is enabled and removed through the fmp_r bit in the option byte. ? in rom devices it is enabled by mask option specified in the option list. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impos- sible to both overwrite and erase program memo- ry. its purpose is to provide advanced security to applications and prevent any change being made to the memory content. warning : once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. write/erase protection is enabled through the fmp_w bit in the option byte. 4.6 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . an1477: emulated da ta eeprom with xflash memory an1576: iap drivers for st7 hdflash or xflash mcus an1575: on board programming methods for st7 hdflash or xflash mcus an1070: checksum self checking capability 4.7 register description flash control/status register (fcsr) read/write reset value: 000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) note: this register is reserved for programming using icp, iap or other programming methods. it controls the xflash programming and erasing op- erations. when an epb or anothe r programming tool is used (in socket or icp mode), the rass keys are sent automatically. 70 00000optlatpgm st72260gx, st72262gx, st72264gx 17/172 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer low power halt and wait modes priority maskable hardware interrupts non-maskable software/hardware interrupts 5.3 cpu registers the 6 cpu registers shown in figure 7 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 7. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value st72260gx, st72262gx, st72264gx 18/172 central processing unit (cont?d) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested usin g the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it?s a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 st72260gx, st72262gx, st72264gx 19/172 central processing unit (cont?d) stack pointer (sp) read/write reset value: 01 7fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 8 ). since the stack is 128 bytes deep, the 8 most sig- nificant bits are forced by hardware. following an mcu reset, or after a re set stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 8 ? when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. ? on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five location s in the stack area. figure 8. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h st72260gx, st72262gx, st72264gx 20/172 6 supply, reset an d clock management the device includes a ran ge of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 10 . for more details, refer to dedicated parametric section. main features optional pll for multiplying the frequency by 2 (not to be used with internal rc oscillator) reset sequence manager (rsm) multi-oscillator cloc k management (mo) ? 4 crystal/ceramic resonator oscillators ? 1 internal rc oscillator system integrity management (si) ? main supply low voltage detector (lvd) ? auxiliary voltage dete ctor (avd) with inter- rupt capability for moni toring the main supply 6.1 phase locked loop if the clock frequency input to the pll is in the 2 to 4 mhz range, the pll can be used to multiply the frequency by two to obtain an f osc2 of 4 to 8 mhz. the pll is enabled by option byte. if the pll is disabled, then f osc2 = f osc /2. caution: the pll is not recommended for appli- cations where timing accuracy is required. see ?pll characteristics? on page 139. figure 9. pll block diagram figure 10. clock, reset and supply block diagram 0 1 pll option bit pll x 2 f osc2 / 2 f osc low voltage detector (lvd) f osc2 auxiliary voltage detector (avd) multi- oscillator (mo) osc1 reset v ss v dd reset sequence manager (rsm) osc2 main clock avd interrupt request controller pll watchdog sicsr timer (wdg) with realtime clock (mcc/rtc) avd avd lvd rf 0 ie 0 wdg rf f osc (option) 0 f f cpu 0 miscr1 register system integrity management slow mode selection to cpu and peripherals st72260gx, st72262gx, st72264gx 21/172 6.2 multi-osc illator (mo) the main clock of the st7 can be generated by four different source types coming from the multi- oscillator block: an external source 5 crystal or ceramic resonator oscillators an internal high frequency rc oscillator each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in table 3 . refer to the electrical characteristics section for more details. caution: the osc1 and/or osc2 pins must not be left unconnected. for the purposes of failure mode and effects analysis, it should be noted that if the osc1 and/or osc2 pins are left unconnect- ed, the st7 main oscillato r may start and, in this configuration, could generate an f osc clock fre- quency in excess of the allowed maximum (>16mhz.), putting the st7 in an unsafe/unde- fined state. the product behaviour must therefore be considered undefined when the osc pins are left unconnected. external clock source in this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. crystal/ceramic oscillators this family of oscillators has the advan tage of pro- ducing a very accurate rate on the main clock of the st7. the selection with in a list of 5 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1 on page 162 for more details on the frequency ranges). in this mode of the multi- oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscil- lator pins in order to minimize output distortion and start-up stabilization ti me. the loading capaci- tance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. internal rc oscillator this oscillator allows a lo w cost solution for the main clock of the st7 using only an internal resis- tor and capaci tor. internal rc oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require ac- curate timing. in this mode, the two oscilla tor pins have to be tied to ground. related documentation an1530: accurate timebase for low cost st7 ap- plications with internal rc. table 3. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7 st72260gx, st72262gx, st72264gx 22/172 6.3 reset sequence manager (rsm) 6.3.1 introduction the reset sequence manager includes three re- set sources as shown in figure 12 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 11 : active phase depending on the reset source 4096 cpu clock cycle delay (selected by option byte) reset vector fetch the 4096 cpu clock cycle delay allows the oscil- lator to stabilise and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay should be selected by op- tion byte to correspond to the stabilization time of the external oscillator us ed in the application. the reset vector fetch phase duration is 2 clock cycles. figure 11. reset sequence phases 6.3.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristic section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 13 ). this de- tection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 12. reset block diagram reset active phase internal reset 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter st72260gx, st72262gx, st72264gx 23/172 reset sequence manager (cont?d) the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. 6.3.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specified for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the reset pin. 6.3.4 internal low voltage detector (lvd) reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd st72260gx, st72262gx, st72264gx 25/172 system integrity management (cont?d) 6.4.2 auxiliary voltage detector (avd) the voltage detector function (avd) is based on an analog comparison between a v it- and v it+ ref- erence value and the v dd main supply. the v it- reference value for falling vo ltage is lower than the v it+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator is directly read- able by the application software through a real time status bit (vdf) in the sicsr register. this bit is read only. caution : the avd functions only if the lvd is en- abled through the option byte. 6.4.2.1 monitoring the v dd main supply the avd voltage threshold va lue is relative to the selected lvd threshold configured by option byte (see section 15.1 on page 162 ). if the avd interrupt is enabled, an interrupt is gen- erated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit toggles). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcon- troller. see figure 15 . the interrupt on the rising edge is used to inform the application that the v dd warning state is over. if the voltage rise time t rv is less than 256 or 4096 cpu cycles (depending on the reset delay select- ed by option byte), no avd interrupt will be gener- ated when v it+(avd) is reached. if t rv is greater than 256 or 4096 cycles then: ? if the avd interrupt is enabled before the v it+(avd) threshold is reached, then 2 avd inter- rupts will be received: the first when the avdie bit is set, and the second when the threshold is reached. ? if the avd interrupt is enabled after the v it+(avd) threshold is reached then only one avd interrupt will occur. figure 15. using the avd to monitor v dd v dd v it+(avd) v it-(avd) avdf bit 0 0 reset value if avdie bit = 1 v hyst avd interrupt request interrupt process interrupt process v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 1 1 t rv voltage rise time st72260gx, st72262gx, st72264gx 26/172 system integrity management (cont?d) 6.4.3 low power modes 6.4.3.1 interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is re- set (rim instruction). mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no st72260gx, st72262gx, st72264gx 27/172 system integrity management (cont?d) 6.4.4 register description system integrity (si) control/status register (sicsr) read/write reset value: 000x 000x (00h) bit 7 = reserved, always read as 0. bit 6 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag changes (toggles). the pending interrupt informa- tion is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled bit 5 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is gen- erated when the avdf bit changes value. 0: v dd over v it+(avd) threshold 1: v dd under v it-(avd) threshold bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 3:1 = reserved, must be kept cleared. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was generat- ed by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. 70 0 avd ie avd f lvd rf 000 wdg rf reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x address (hex.) register label 76543210 0025h sicsr reset value 0 avdie 0 avdf 0 lvdrf x000 wdgrf x st72260gx, st72262gx, st72264gx 28/172 7 interrupts 7.1 introduction the st7 enhanced interrupt management pro- vides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrup t priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 2 non-maskable ev ents: reset and trap this interrupt management is based on: ? bit 5 and bit 3 of the cpu cc register (i1:0), ? interrupt software priority registers (isprx), ? fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with th e standard (not nest- ed) st7 interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt so ftware priority level of each interrupt vector (see table 4 ). the process- ing flow is shown in figure 16 when an interrupt request has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to ?interrupt mapping? table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the pr evious level will resume. table 4. interrupt software priority levels figure 16. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset pending instruction i1:0 from stack load pc from interrupt vector y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt st72260gx, st72262gx, st72264gx 29/172 interrupts (cont?d) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: ? the highest software priority interrupt is serviced, ? if several interr upts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 17 describes this decision process. figure 17. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : reset and trap are non-maskable and they can be considered as having the highest soft- ware priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset and trap) and the maskable type (exter- nal or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 16 ). after stacking the pc, x, a and cc registers (except for r eset), the co rresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart on figure 16 as a tli. reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitiv ity is software selectable through the miscellaneous registers (miscrx). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt vector request an interrupt simulta- neously, the interrupt vect or will be serviced. soft- ware can read the pin levels to identify which pin(s) are the source of the interrupt. if several input pins ar e selected simultaneously as interrupt source, these are logically nanded. for this reason if one of the interrupt pins is tied low, it masks the other ones. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the ?interrupt mapping? table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will theref ore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced st72260gx, st72262gx, st72264gx 30/172 interrupts (cont?d) 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit the halt modes (see column ?exit from halt? in ?interrupt mapping? table). when several pending interrupts are present while exiting halt mode, the first one serviced can only be an inter- rupt with exit from halt mode capability and it is selected through the same decision process shown in figure 17 . note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent & nested management the following figure 18 and figure 19 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 19 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0. the software priority is giv- en for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. note: tli (top level interrupt) is not available in this product. related documentation an1044: multiple interrupt source management for st7 mcus figure 18. concurrent interrupt management figure 19. nested interrupt management main it4 it2 it1 tli it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 tli it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 tli main it0 it2 it1 it4 tli it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes st72260gx, st72262gx, st72264gx 31/172 interrupts (cont?d) 7.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see ?interrupt dedicated instruction set? table). *note : trap and reset events are non maska- ble sources and can interrupt a level 3 program. interrupt software priority regis- ters (isprx) read/write (bits 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. ? each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. ? each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. ? level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the reset and trap vectors have no software priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah ei0 fff9h-fff8h ei1 ... ... ffe1h-ffe0h not used st72260gx, st72262gx, st72264gx 32/172 interrupts (cont?d) table 5. interrupt mapping note 1. configurable by option byte. table 6. nested interrupts register map and reset values n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 ei0 external interrupt port a7..0 (c5..0 1 ) yes fffah-fffbh 1 ei1 external interrupt port b7..0 (c5..0 1 ) fff8h-fff9h 2 not used fff6h-fff7h 3 spi spi peripheral interrupts spisr yes fff4h-fff5h 4 timer a timer a peripheral interrupts tasr no fff2h-fff3h 5 mcc time base interrupt mccsr yes fff0h-fff1h 6 timer b timer b peripheral interrupts tbsr no ffeeh-ffefh 7 avd auxiliary voltage detector interrupt sicsr ffech-ffedh 8 not used ffeah-ffebh 9 not used ffe8h-ffe9h 10 sci sci peripheral interrupt scisr no ffe6h-ffe7h 11 i 2 c i 2 c peripheral interrupt i2csrx no ffe4h-ffe5h 12 not used ffe2h-ffe3h 13 not used ffe0h-ffe1h address (hex.) register label 76543210 001ch ispr0 reset value spi not used ei1 ei0 i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 1 i1_0 1 i0_0 1 001dh ispr1 reset value avd timerb mcc timera i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 001eh ispr2 reset value i 2 c sci not used not used i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 001fh ispr3 reset value1111 not used not used i1_13 1 i0_13 1 i1_12 1 i0_12 1 st72260gx, st72262gx, st72264gx 33/172 8 power saving modes 8.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, three main power saving modes are implemented in the st7 (see figure 20 ). after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by callin g the specific st7 software instruction whose action depends on the oscillator status. figure 20. power saving mode transitions 8.2 slow mode this mode has two targets: ? to reduce power consumption by decreasing the internal clock in the device, ? to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the misr1 register: the sms bit which enables or dis- ables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the oscillato r frequency can be divid- ed by 4, 8, 16 or 32 instead of 2 in normal operat- ing mode. the cpu and peripherals are clocked at this lower frequency. note : slow-wait mode is activated when enter- ring the wait mode while the device is already in slow mode. figure 21. slow mode clock transitions power consumption wait slow run halt high low slow wait 00 01 sms cp1:0 f cpu new slow normal run mode miscr1 frequency request request f osc2 f osc2 /2 f osc2 /4 f osc2 st72260gx, st72262gx, st72264gx 34/172 power saving modes (cont?d) 8.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? st7 software instruction. all peripherals remain active. during wait mode, the i [1:0] bits in the cc register are forced to ?10b? , to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wa it mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 22 . figure 22. wait mode flowchart note: 1. before servicing an inte rrupt, the cc register is pushed on the stack. the i[1:0] bits in the cc reg- ister are set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 1 on cpu oscillator peripherals i[1:0] bits on on xx 1) on 4096 cpu clock cycle delay st72260gx, st72262gx, st72264gx 35/172 8.4 active-halt and halt modes active-halt and halt modes are the two low- est power consumption modes of the mcu. they are both entered by executing the ?halt? instruc- tion. the decision to enter either in active-halt or halt mode is given by the mcc/rtc interrupt enable flag (oie bit in mccsr register). 8.4.1 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the ?halt? in- struction when the oie bit of the main clock con- troller status register (mccsr) is set. the mcu can exit active-halt mode on recep- tion of either an mcc/rtc interrupt, a specific in- terrupt (see table 5, ?interrupt mapping,? on page 32 ) or a reset. when exiting active-halt mode by means of an interrupt, no 4096 cpu cy- cle delay occurs. the cpu resumes operation by servicing the interrupt or by fetching the reset vec- tor which woke it up (see figure 24 ). when entering active-halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable in- terrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, on ly the main oscillator and its associated counter (mcc/rtc) are run- ning to keep a wake-up time base. all other periph- erals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). the safeguard against staying locked in active- halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capability of one of the oscillators is selected (mccsr.oie bit set), entering active-halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 23. active-halt timing overview figure 24. active-halt mode flowchart notes: 1. this delay occurs only if the mcu exits active- halt mode by means of a reset. 2. peripheral clocked with an external clock source can still be active. 3. only the mcc/rtc inte rrupt and some specific interrupts can exit the mcu from active-halt mode (such as external interrupt). refer to table 5, ?interrupt mapping,? on page 32 for more details. 4. before servicing an inte rrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and restored when the cc register is popped. mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active-halt mode halt run run 4096 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [mccsr.oie=1] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 4096 cpu clock cycle delay (mccsr.oie=1) st72260gx, st72262gx, st72264gx 36/172 power saving modes (cont?d) 8.5 halt mode the halt mode is the lo west power consumption mode of the mcu. it is entered by executing the st7 halt instruction (see figure 26 ). the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 5, ?interrupt mapping,? on page 32 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediat ely turned on and the 4096 cpu cycle delay is us ed to stabilize the os- cillator. after th e start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 25 ). when entering halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immediately. in the halt mode the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of wa tchdog operation with halt mode is configured by the ?wdghalt? op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see section 15.1 "option bytes" on page 162 for more details). figure 25. halt mode timing overview figure 26. halt mode flowchart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 5, ?interrupt mapping,? on page 32 for more details. 4. before servicing an inte rrupt, the cc register is pushed on the stack. the i[1:0] bits in the cc reg- ister are set during the interrupt routine and cleared when the cc register is popped. halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 1 on cpu oscillator peripherals i[1:0] bits on on xx 4) on 4096 cpu clock cycle delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 st72260gx, st72262gx, st72264gx 37/172 power saving modes (cont?d) 8.5.0.1 halt mode recommendations ? make sure that an external event is available to wake up the microcontroller from halt mode. ? when using an external interrupt to wake up the microcontroller, reinitia lize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. ? for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. ? as the halt instruction clears the interrupt mask in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits be- fore executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corre- sponding to the wake-up event (reset or external interrupt). related documentation an 980: st7 keypad decoding techniques, im- plementing wake-up on keystroke an1014: how to minimize the st7 power con- sumption an1605: using an active rc to wakeup the st7lite0 from power saving mode st72260gx, st72262gx, st72264gx 38/172 9 i/o ports 9.1 introduction the i/o ports allow data transfer. an i/o port can contain up to 8 pins. each pin can be programmed independently either as a digital input or digital output. in addition, specific pins may have several other functions. these functions can include exter- nal interrupt, alternate signal input/output for on- chip peripherals or analog input. 9.2 functional description a data register (dr) and a data direction regis- ter (ddr) are always associated with each port. the option register (or) , which allows input/out- put options, may or may not be implemented. the following description take s into account the or register. refer to the port configuration table for device specific information. an i/o pin is programmed using the corresponding bits in the ddr, dr and or registers: bit x corre- sponding to pin x of the port. figure 27 shows the generic i/o block diagram. 9.2.1 input modes clearing the ddrx bit selects input mode. in this mode, reading its dr bit returns the digital value from that i/o pin. if an or bit is available, different input modes can be configured by software: floating or pull-up. re- fer to i/o port implementation section for configu- ration. notes : 1. writing to the dr modifies the latch value but does not change the state of the input pin. 2. do not use read/mod ify/write instructions (bset/bres) to modify the dr register. external interrupt function depending on the device, setting the orx bit while in input mode can configure an i/o as an input with interrupt. in this configuration, a signal edge or lev- el input on the i/o generates an interrupt request via the corresponding interrupt vector (eix). falling or rising edge sens itivity is programmed in- dependently for each interrupt vector. the exter- nal interrupt control register (eicr) or the miscel- laneous register controls this sensitivity, depend- ing on the device. a device may have up to 7 external interrupts. several pins may be tied to one external interrupt vector. refer to pin description to see which ports have external interrupts. if several i/o interrupt pins on the same interrupt vector are selected simultaneously, they are logi- cally combined. for this reason if one of the inter- rupt pins is tied low, it may mask the others. external interrupts are hardware interrupts. fetch- ing the corresponding interrupt vector automatical- ly clears the request latch. modifying the sensitivity bits will clear any pending interrupts. 9.2.2 output modes setting the ddrx bit selects output mode. writing to the dr bits applies a digital value to the i/o through the latch. reading the dr bits returns the previously stored value. if an or bit is available, different output modes can be selected by software: push-pull or open- drain. refer to i/o port implementation section for configuration. dr value and output pin status 9.2.3 alternate functions many st7s i/os have one or more alternate func- tions. these may include output signals from, or input signals to, on-chip peripherals. the device pin description table describes which peripheral signals can be input/output to which ports. a signal coming from an on-chip peripheral can be output on an i/o. to do this, enable the on-chip peripheral as an output (enable bit in the peripher- al?s control register). the peripheral configures the i/o as an output and takes priority over standard i/ o programming. the i/o?s state is readable by ad- dressing the corresponding i/o data register. configuring an i/o as floating enables alternate function input. it is not recommended to configure an i/o as pull-up as this will increase current con- sumption. before using an i/o as an alternate in- put, configure it without interrupt. otherwise spuri- ous interrupts can occur. configure an i/o as input floating for an on-chip peripheral signal which can be input and output. caution : i/os which can be configured as both an analog and digital alternate function need special atten- tion. the user must control the peripherals so that the signals do not arrive at the same time on the same pin. if an external clock is used, only the clock alternate function should be employed on that i/o pin and not the other alternate function. dr push-pull open-drain 0v ol v ol 1v oh floating st72260gx, st72262gx, st72264gx 39/172 i/o ports (cont?d) figure 27. i/o port general block diagram table 7. i/o port mode options legend :ni - not implemented off - implemented not activated on - implemented and activated note: the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ol is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external request (ei x ) interrupt sensitivity selection cmos schmitt trigger register access bit from on-chip periphera l to on-chip peripheral note : refer to the port configuration table for device specific information. combinational logic st72260gx, st72262gx, st72264gx 40/172 i/o ports (cont?d) table 8. i/o configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate functi on output status. 2. when the i/o port is in output configuration and th e associated alternate function is enabled as an input, the alternate function reads the pin stat us given by the dr register content. 3. for true open drain, these elements are not implemented. hardware configuration input 1) open-drain output 2) push-pull output 2) note 3 condition pad v dd r pu external interrupt polarity data b u s pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register condition alternate input analog input to on-chip peripheral combinational logic note 3 pad r pu data bus dr dr register access r/w v dd register pad r pu data b u s dr dr register access r/w v dd alternate alternate enable output register bit from on-chip periphera l note 3 st72260gx, st72262gx, st72264gx 41/172 i/o ports (cont?d) analog alternate function configure the i/o as floating input to use an adc input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the adc input. analog recommendations do not change the voltage level or loading on any i/o while conversion is in progress. do not have clocking pins located close to a selected analog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 9.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific i/o port features such as adc input or open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 28 . other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation. figure 28. interrupt i/o port state transitions 9.4 unused i/o pins unused i/o pins must be connected to fixed volt- age levels. refer to section 13.8 . 9.5 low power modes 9.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and if the i bit in the cc register is cleared (rim instruction). related documentation an 970: spi communication between st7 and eeprom an1045: s/w implementation of i2c bus master an1048: software lcd driver 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes st72260gx, st72262gx, st72264gx 42/172 i/o ports (cont?d) 9.7 device-specific i/o port configuration the i/o port register configurations are summa- rised as follows. interrupt ports pa7, pa5, pa3:0, pb7:0, pc5:0 (with pull-up) true open drain interrupt ports pa6, pa4 (without pull-up) table 9. port configuration mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 open drain (high sink ports) 1 x port pin name input (ddr = 0) output (ddr = 1) or = 0 or = 1 or = 0 or = 1 high-sink port a pa7 floating pull-up interrupt open drain push-pull yes pa6 floating floating in terrupt true open-drain pa5 floating pull-up interrupt open drain push-pull pa4 floating floating in terrupt true open-drain pa3:0 floating pull-up interrupt open drain push-pull port b pb7:0 floating pull-up interrupt open drain push-pull no port c pc5:0 floating pull-up interrupt open drain push-pull st72260gx, st72262gx, st72264gx 43/172 i/o ports (cont?d) 9.8 i/o port register description data register (dr) port x data register pxdr with x = a, b or c. read/write reset value: 0000 0000 (00h) bits 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows always having the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a, b or c. read/write reset value: 0000 0000 (00h) bits 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register pxor with x = a, b or c. read/write reset value: 0000 0000 (00h) bits 7:0 = o[7:0] option register 8 bits. for specific i/o pins, this register is not implement- ed. in this case the ddr register is enough to se- lect the i/o pin configuration. the or register allows to distinguish: in input mode if the pull-up with in terrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. each bit is set and cleared by software. input mode: 0: floating input 1: pull-up input with or without interrupt output mode: 0: output open drain (with p-buffer unactivated) 1: output push-pull (when available) 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0 st72260gx, st72262gx, st72264gx 44/172 i/o ports (cont?d) table 10. i/o port register map and reset values address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h pcdr msb lsb 0001h pcddr 0002h pcor 0004h pbdr msb lsb 0005h pbddr 0006h pbor 0008h padr msb lsb 0009h paddr 000ah paor st72260gx, st72262gx, st72264gx 45/172 10 miscellaneous registers the miscellaneous registers allow control over several different features such as the external in- terrupts or the i/o alternate functions. 10.1 i/o port interrupt sensitivity the external interrupt se nsitivity is controlled by the isxx bits of the miscellaneous register and the option byte. this control allows you to have two fully independent external interrupt source sensitivities with configur able sources (using the extit option bit) as shown in figure 29 and fig- ure 30 . each external interrupt source can be generated on four different events on the pin: falling edge rising edge falling and rising edge falling edge and low level to guarantee correct functionality, the sensitivity bits in the miscr1 register must be modified only when the i[1:0] bits in the cc register are set to 1 (interrupt masked). see section 9.8 "i/o port register description" on page 43 and sec- tion 10.3 "miscellaneous register de- scription" on page 46 for more details on the programming. 10.2 i/o port alternate functions the miscr registers manage four i/o port miscel- laneous alternate functions: main clock signal (f cpu ) output on pc2 spi pin configuration: ?ss pin internal control to use the pb7 i/o port function while the spi is active. ? master output capability on the mosi pin (pb4) deactivated while the spi is active. ? slave output capabilit y on the miso pin (pb5) deactivated while the spi is active. these functions are described in detail in the sec- tion 10.3 "miscellaneous register de- scription" on page 46 . figure 29. ext. interrupt sensitivity (extit=0) figure 30. ext. interrupt sensitivity (extit=1) ei0 interrupt source is00 is01 miscr1 sensitivity control pa7 pa0 pc5 pc0 pb7 pb0 is10 is11 miscr1 sensitivity control ei1 interrupt source pa7 pa0 is00 is01 miscr1 sensitivity control ei0 interrupt source ei1 interrupt source is10 is11 miscr1 sensitivity control pb7 pb0 pc5 pc0 st72260gx, st72262gx, st72264gx 46/172 miscellaneous registers (cont?d) 10.3 miscellaneous register description miscellaneous register 1 (miscr1) read/write reset value: 0000 0000 (00h) bits 7:6 = is1[1:0] ei1 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the ei1 external interrupts. these two bits can be written only when the i[1:0] bits in the cc register are set to 1 (interrupt masked). ei1: port b (c optional) bit 5 = mco main clock out selection this bit enables the mco al ternate function on the pc2 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) bits 4:3 = is0[1:0] ei0 sensitivity the interrupt sensitivity, defined using the is0[1:0] bits, is applied to the ei0 external interrupts. these two bits can be written only when the i[1:0] bits in- the cc register are set to 1 (interrupt masked). ei0: port a (c optional) bits 2:1 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the various slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc2 1: slow mode. f cpu is given by cp1, cp0 see low power consumption mode and mcc chapters for more details. 70 is11 is10 mco is01 is00 cp1 cp0 sms external interrupt sensitivity is11 is10 falling edge & low level 0 0 rising edge only 0 1 falling edge only 1 0 rising and falling edge 1 1 external interrupt sensitivity is01 is00 falling edge & low level 0 0 rising edge only 0 1 falling edge only 1 0 rising and falling edge 1 1 f cpu in slow mode cp1 cp0 f osc2 / 2 0 0 f osc2 / 4 1 0 f osc2 / 8 0 1 f osc2 / 16 1 1 st72260gx, st72262gx, st72264gx 47/172 miscellaneous registers (cont?d) miscellaneous register 2 (miscr2) read/write reset value: 0000 0000 (00h) caution: this register has been provided for com- patibility with the st72254 family only. the same bits are available in the spicsr register. new ap- plications must use the spicsr register. do not use both registers, this will cause the spi to mal- function. bits 7:4 = reserved always read as 0 bits 3 = mod spi master output disable this bit is set and cleared by software. when set, it disables the spi master (mosi) output signal. 0: spi master output enabled. 1: spi master output disabled. bit 2 = sod spi slave output disable this bit is set and cleared by software. when set it disable the spi slave (miso) output signal. 0: spi slave output enabled. 1: spi slave output disabled. bit 1 = ssm ss mode selection this bit is set and cleared by software. 0: normal mode - the level of the spi ss signal is input from the external ss pin. 1: i/o mode, the level of the spi ss signal is read from the ssi bit. bit 0 = ssi ss internal mode this bit replaces the ss pin of the spi when the ssm bit is set to 1. (see spi description). it is set and cleared by software. table 11. miscellaneous register map and reset values 70 0 0 0 0 mod sod ssm ssi address (hex.) register label 76543210 0020h miscr1 reset value is11 0 is10 0 mco 0 is01 0 is00 0 cp1 0 cp0 0 sms 0 0040h miscr2 reset value0000 mod 0 sod 0 ssm 0 ssi 0 st72260gx, st72262gx, st72264gx 48/172 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter?s contents before the t6 bit be- comes cleared. 11.1.2 main features programmable free-running downcounter programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 11.1.3 functional description the counter value stored in the watchdog control register (wdgcr bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low th e reset pin for typically 500ns. the application program must write in the wdgcr register at regular intervals during normal operation to prevent an mcu reset. this down- counter is free-running: it counts down even if the watchdog is disabled. the value to be stored in the wdgcr register must be between ffh and c0h: ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an imme- diate reset ? the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 32. ap- proximate timeout duration ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writ- ing to the wdgcr register (see figure 33 ). following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. figure 31. watchdog block diagram reset wdga 6-bit downcounter (cnt) f osc2 t6 t0 wdg prescaler watchdog control register (wdgcr) div 4 t1 t2 t3 t4 t5 12-bit mcc rtc counter msb lsb div 64 0 5 6 11 mcc/rtc tb[1:0] bits (mccsr register) st72260gx, st72262gx, st72264gx 49/172 watchdog timer (cont?d) 11.1.4 how to program the watchdog timeout figure 32 shows the linear relationship between the 6-bit value to be loaded in the watchdog coun- ter (cnt) and the resulting timeout duration in mil- liseconds. this can be used for a quick calculation without taking the timing variations into account. if more precision is needed, use the formulae in fig- ure 33 . caution: when writing to the wdgcr register, al- ways write 1 in the t6 bit to avoid generating an immediate reset. figure 32. approximate timeout duration cnt value (hex.) watchdog timeout (ms) @ 8 mhz. f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114 st72260gx, st72262gx, st72264gx 50/172 watchdog timer (cont?d) figure 33. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below depending on the timebase selected by the tb[1:0] bits in the mccsr register to calculate the minimum watchdog timeout (t min ): if then else to calculate the maximum watchdog timeout (t max ): if then else note: in the above formulae, division results must be rounded down to the next integer value. example: with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr timebase msb lsb 0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54 value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 + = t min t min0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = cnt msb 4 ------------- t max t max0 16384 cnt t osc2 + = t max t max0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = st72260gx, st72262gx, st72264gx 51/172 watchdog timer (cont?d) 11.1.5 low power modes 11.1.6 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to the option byte description. 11.1.7 using halt mode with the wdg (wdghalt option) the following recomme ndation applies if halt mode is used when the watchdog is enabled. ? before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. 11.1.8 interrupts none. 11.1.9 register description control register (wdgcr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit counter (msb to lsb). these bits contain the value of the watchdog counter. it is decremented every 16384 f osc2 cy- cles (approx.). a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). mode description slow no effect on watchdog. wait no effect on watchdog. halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watch- dog counter is decremented once and t hen stops counting and is no longer able to generate a watchdog reset until the mcu receives an external inter- rupt or a reset. if an external interrupt is received, the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is gener ated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. for applica- tion recommendations see section 11.1.7 below. 0 1 a reset is generated. 1x no reset is generated. the mcu ente rs active halt mode. the watchdog counter is not decremented. it stop counting. when the mcu receives an oscillator interrupt or external inte rrupt, the watchdog restarts counting im- mediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks. 70 wdga t6 t5 t4 t3 t2 t1 t0 st72260gx, st72262gx, st72264gx 52/172 table 12. watchdog timer register map and reset values address (hex.) register label 76543210 0024h wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 st72260gx, st72262gx, st72264gx 53/172 11.2 main clock controller with real time clock (mcc/rtc) the main clock controller consists of a real time clock timer with interrupt capability 11.2.1 real time clock timer (rtc) the counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. four different time bases depend- ing directly on f osc2 are available. the whole functionality is controlled by four bits of the mcc- sr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active-halt mode when the halt instruction is executed. see section 8.4 "active-halt and halt modes" on page 35 for more details. figure 34. main clock contro ller (mcc/rtc) block diagram mcc/rtc interrupt tb1 tb0 oie oif mccsr rtc counter f osc2 to watchdog st72260gx, st72262gx, st72264gx 54/172 main clock controller with real time clock (cont?d) 11.2.2 low power modes 11.2.3 interrupts the mcc/rtc interrupt event generates an inter- rupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). note : the mcc/rtc interrupt wakes up the mcu from active-halt mode, not from halt mode. 11.2.4 register description mcc control/status register (mccsr) read/write reset value: 0000 0000 (00h ) bit 7:4 = reserved bit 3:2 = tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid an unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active- halt mode. when this bit is set, calling the st7 software halt instruction enters the active-halt power saving mode . bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the csr register. it indicates when set that the main oscillator has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution : the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. table 13. main clock controller register map and reset values mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt cause the device to exit from wait mode. active- halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen. mcc/rtc interrupt cause the device to exit from active-halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with ?exit from halt? capability. interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no 1) 70 0000tb1tb0oieoif counter prescaler time base tb1 tb0 f osc2 =4mhz f osc2 =8mhz 16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0 200000 50ms 25ms 1 1 address (hex.) register label 76543210 0025h sicsr reset value 0 avdie 0 avdf 0 lvdrf x000 wdgrf x 0026h mccsr reset value0000 tb1 0 tb0 0 oie 0 oif 0 st72260gx, st72262gx, st72264gx 55/172 11.3 16-bit timer 11.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few micros econds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some devices of the st7 family have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are syn- chronized after a device reset as long as the timer clock frequencies are not modified. this description covers one or two 16-bit timers. in the devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 11.3.2 main features programmable prescaler: f cpu divided by 2, 4 or 8. overflow status flag and maskable interrupt external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge output compare functions with ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt input capture functions with ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 35 . *note: some timer pins may not available (not bonded) in some devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be ?1?. 11.3.3 functional description 11.3.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): ? counter high register (chr) is the most sig- nificant byte (ms byte). ? counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) ? alternate counter high register (achr) is the m ost significant byte (ms byte). ? alternate counter low r egister (aclr) is the least significant byte (ls byte ). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 14 clock control bits . the value in the counter register re- peats every 131 072, 262 144 or 524 288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. st72260gx, st72262gx, st72264gx 56/172 16-bit timer (cont?d) figure 35. timer block diagram 16-bit timer peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) csr st72260gx, st72262gx, st72264gx 57/172 16-bit timer (cont?d) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value rema ins unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: ? the tof bit of the sr register is set. ? a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cl eared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (device awakened by an interrupt) or from the reset count (device awakened by a reset). 11.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchron ised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + ? t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte st72260gx, st72262gx, st72264gx 58/172 16-bit timer (cont?d) figure 36. counter timing diagram, internal clock divided by 2 figure 37. counter timing diagram, internal clock divided by 4 figure 38. counter timing diagram, internal clock divided by 8 note: the device is in reset state when the internal rese t signal is high, when it is low the device is run- ning. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 st72260gx, st72262gx, st72264gx 59/172 16-bit timer (cont?d) 11.3.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function select the follow- ing in the cr2 register: ? select the timer clock (cc[1:0]) (see table 14 clock control bits ). ? select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input). and select the following in the cr1 register: ? set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input). when an input capture occurs: ? icf i bit is set. ? the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 40 ). ? a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with interrupt in order to measure event that go beyond the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr st72260gx, st72262gx, st72264gx 60/172 16-bit timer (cont?d) figure 39. input capture block diagram figure 40. input capture timing diagram note: the time between an event on the icapi pin and the appearance of the corresponding flag is from 2 to 3 cpu clock cycles. this depends on the moment when the icap event happens relative to the timer clock. icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: the active edge is the rising edge. st72260gx, st72262gx, st72264gx 61/172 16-bit timer (cont?d) 11.3.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: ? assigns pins with a prog rammable value if the ocie bit is set ? sets a flag in the status register ? generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: ? set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. ? select the timer clock (cc[1:0]) (see table 14 clock control bits ). and select the following in the cr1 register: ? select the olvl i bit to applied to the ocmp i pins after the match occurs. ? set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ? ocf i bit is set. ? the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). ? a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: ? t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 14 clock control bits ) if the timer clock is an external clock, the formula is: where: ? t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: ? write to the oc i hr register (further compares are inhibited). ? read the sr register (first step of the clearance of the ocf i bit, which may be already set). ? write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr ? oc i r = ? t * f cpu presc ? oc i r = ? t * f ext st72260gx, st72262gx, st72264gx 62/172 16-bit timer (cont?d) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 42 on page 63 ). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 43 on page 63 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in both one pulse mode and pwm mode. figure 41. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 st72260gx, st72262gx, st72264gx 63/172 16-bit timer (cont?d) figure 42. output compare timing diagram, f timer =f cpu /2 figure 43. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i ) st72260gx, st72262gx, st72264gx 64/172 16-bit timer (cont?d) 11.3.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see table 14 clock control bits ). when a valid event occurs on the icap1 pin, the counter value is loaded in the icr1 register. the counter is then initialized to fffch, the olvl2 bit is output on the ocmp1 pin and the icf1 bit is set. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 14 clock control bits ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 44 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a co ntinuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an out- put waveform because the level olvl2 is dedi- cated to the one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72260gx, st72262gx, st72264gx 65/172 16-bit timer (cont?d) figure 44. one pulse mode timing example figure 45. pulse width modul ation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 01f8 01f8 2ed3 ic1r counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2 st72260gx, st72262gx, st72264gx 66/172 16-bit timer (cont?d) 11.3.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r regis- ter, and so this functionality can not be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values writ- ten in the oc1r and oc2r registers are loaded in their respective shadow registers (double buffer) only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). the shadow registers contain the reference values for comparison in pwm ?double buffering? mode. note: there is a locking mechanism for transfer- ring the ocir value to the buffer. after a write to the ocihr register, transf er of the new compare value to the buffer is inhibited until ocilr is also written. unlike in output compare mode, the compare function is always enabled in pwm mode. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if (olvl1=0 and olvl2=1) using the formula in the oppo- site column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. ? using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see table 14 clock control bits ). if olvl1=1 and olvl2=0 the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a conti nuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 14 clock control bits ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 45 ) notes: 1. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 2. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72260gx, st72262gx, st72264gx 67/172 16-bit timer (cont?d) 3. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 4. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 11.3.4 low power modes 11.3.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 11.3.6 summary of timer modes 1) see note 4 in section 11.3.3.5 "one pulse mode" on page 64 2) see note 5 in section 11.3.3.5 "one pulse mode" on page 64 3) see note 4 in section 11.3.3.6 "pulse width modulation mode" on page 66 mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer regist ers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting re sumes from the previous count when the device is woken up by an interrupt with ?exit from halt mode? capab ility or from the counter reset value when the device is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detecti on circuitry is armed. consequent- ly, when the device is woken up by an interrupt with ?exit from halt mode? capability, the icf i bit is set, and the counter value present when exiting fr om halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no st72260gx, st72262gx, st72264gx 68/172 16-bit timer (cont?d) 11.3.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no succes sful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge tr iggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 st72260gx, st72262gx, st72264gx 69/172 16-bit timer (cont?d) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer re- mains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer re- mains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 14. clock control bits note : if the external clock pi n is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge tr iggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 11 st72260gx, st72262gx, st72264gx 70/172 16-bit timer (cont?d) control/status register (csr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2 = timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disa- bled the output functions (ocmp1 and ocmp2 pins) to reduce power cons umption. access to the timer registers is still ava ilable, allowing the timer configuration to be changed while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, mu st be kept cleared. 70 icf1 ocf1 tof icf2 ocf2 timd 0 0 st72260gx, st72262gx, st72264gx 71/172 16-bit timer (cont?d) input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72260gx, st72262gx, st72264gx 72/172 16-bit timer (cont?d) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72260gx, st72262gx, st72264gx 73/172 16-bit timer (cont?d) table 15. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 csr reset value icf1 x ocf1 x tof x icf2 x ocf2 x timd 0 - x - x timer a: 34 timer b: 44 ic1hr reset value msb - ------ lsb - timer a: 35 timer b: 45 ic1lr reset value msb - ------ lsb - timer a: 36 timer b: 46 oc1hr reset value msb - ------ lsb - timer a: 37 timer b: 47 oc1lr reset value msb - ------ lsb - timer a: 3e timer b: 4e oc2hr reset value msb - ------ lsb - timer a: 3f timer b: 4f oc2lr reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ichr2 reset value msb - ------ lsb - timer a: 3d timer b: 4d iclr2 reset value msb - ------ lsb - st72260gx, st72262gx, st72264gx 74/172 16-bit timer (cont?d) related documentation an 973: sci software communications using 16- bit timer an 974: real time clock with st7 timer output compare an 976: driving a buzzer through the st7 timer pwm function an1041: using st7 pwm signal to generate ana- log input (sinusoid) an1046: uart emulation software an1078: pwm duty cycle switch implementing true 0 or 100 per cent duty cycle an1504: starting a pwm signal directly at high level using the st7 16-bit timer st72260gx, st72262gx, st72264gx 75/172 11.4 serial peripheral interface (spi) 11.4.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation six master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 general description figure 46 shows the serial peripheral interface (spi) block diagram. there are 3 registers: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through 4 pins: ? miso: master in / slave out data ? mosi: master out / slave in data ? sck: serial clock out by spi masters and in- put by spi slaves ?ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master device . st72260gx, st72262gx, st72264gx 76/172 serial peripheral interface (cont?d) figure 46. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 st72260gx, st72262gx, st72264gx 77/172 serial peripheral interface (cont?d) 11.4.3.1 functional description a basic example of inte rconnections between a single master and a sing le slave is illustrated in figure 47 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is alwa ys initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this imp lies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 50 ) but master and slave must be programmed with the same timing mode. figure 47. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software st72260gx, st72262gx, st72264gx 78/172 serial peripheral interface (cont?d) 11.4.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 49 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ?ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 48 ): if cpha=1 (data latched on 2nd clock edge): ?ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): ?ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 11.4.5.3 ). figure 48. generic ss timing diagram figure 49. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin st72260gx, st72262gx, st72264gx 79/172 serial peripheral interface (cont?d) 11.4.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following steps in order (if the spicsr register is not written first, the spicr register setting (mstr bit ) may be not taken into account): 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 50 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. 11.4.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 11.4.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 50 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in section 11.4.3.2 and figure 48 . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to enable the spi i/o functions. 11.4.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spics r register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 11.4.5.2 ). st72260gx, st72262gx, st72264gx 80/172 serial peripheral interface (cont?d) 11.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 50 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 50 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 50. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3bit 2bit 1lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) st72260gx, st72262gx, st72264gx 81/172 serial peripheral interface (cont?d) 11.4.5 error flags 11.4.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. ? the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multi master configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multi-master conflic t and allows software to handle this using an interrupt routine and either perform to a reset or return to an application de- fault state. 11.4.5.2 overrun condition (ovr) an overrun condition occurs, when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: ? the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 11.4.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 11.4.3.2 "slave select management" on page 78 . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the cpu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 51 ). figure 51. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result st72260gx, st72262gx, st72264gx 82/172 serial peripheral interface (cont?d) 11.4.5.4 single master and multimaster configurations there are two types of spi systems: ? single master system ? multimaster system single master system a typical single master system may be configured, using a device as the master and four device s as slaves (see figure 52 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previo us byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system ma y also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. figure 52. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device st72260gx, st72262gx, st72264gx 83/172 serial peripheral interface (cont?d) 11.4.6 low power modes 11.4.6.1 using the spi to wake-up the device from halt mode in slave configuration, the spi is able to wake-up the device from halt mode through a spif inter- rupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per- form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake-up the device from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the device enters halt mode. so if slave se- lection is configured as external (see section 11.4.3.2 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 11.4.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events caus e the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from the spidr r egister when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overru n error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of trans- fer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no st72260gx, st72262gx, st72264gx 84/172 serial peripheral interface (cont?d) 11.4.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or over- run error occurs (spif=1, modf=1 or ovr=1 in the spicsr register) bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.4.5.1 "master mode fault (modf)" on page 81 ). the spe bit is cleared by reset, so the spi periphera l is not initially connect- ed to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 16 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.4.5.1 "master mode fault (modf)" on page 81 ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 16. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 st72260gx, st72262gx, st72264gx 85/172 serial peripheral interface (cont?d) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr regist er. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision stat us (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 51 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 11.4.5.2 ). an interrupt is generated if spie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 11.4.5.1 "master mode fault (modf)" on page 81 ). an spi interrupt can be generated if spie=1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf=1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 11.4.3.2 "slave select management" on page 78 . 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will init iate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 46 ). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0 st72260gx, st72262gx, st72264gx 86/172 serial peripheral interface (cont?d) table 17. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spicsr reset value spif 0 wcol 0 or 0 modf 00 sod 0 ssm 0 ssi 0 st72260gx, st72262gx, st72264gx 87/172 11.5 serial communications interface (sci) 11.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. 11.5.2 main features full duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmit and receive baud rates up to 500k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags two receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver four error detection flags: ? overrun error ? noise error ? frame error ? parity error five interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 11.5.3 general description the interface is externally connected to another device by two pins (see figure 54 ): ? tdo: transmit data output. when the transmit- ter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. ? rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: ? an idle line prior to transmission or reception ? a start bit ? a data word (8 or 9 bits) least significant bit first ? a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: ? a conventional type for commonly-used baud rates, ? an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. st72260gx, st72262gx, st72264gx 88/172 serial communications interface (cont?d) figure 53. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt cr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2 st72260gx, st72262gx, st72264gx 89/172 serial communications interface (cont?d) 11.5.4 functional description the block diagram of the serial control interface, is shown in figure 53 . it contains 6 dedicated reg- isters: ? two control registers (scicr1 & scicr2) ? a status register (scisr) ? a baud rate register (scibrr) ? an extended prescaler receiver register (scier- pr) ? an extended prescaler transmitter register (sci- etpr) refer to the register descriptions in section 11.5.7 for the definitions of each bit. 11.5.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 reg- ister (see figure 53 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 54. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame break frame start bit extra ?1? data frame next data frame next data frame st72260gx, st72262gx, st72264gx 90/172 serial communications interface (cont?d) 11.5.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) be- tween the internal bus and the transmit shift regis- ter (see figure 53 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scietpr registers. ? set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. ? access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: ? the tdr register is empty. ? the data transfer is beginning. ? the next data can be written in the scidr regis- ter without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the scidr register places the data di- rectly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shift register with a break character. the break frame length depends on the m bit (see figure 54 ). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the scidr. st72260gx, st72262gx, st72264gx 91/172 serial communications interface (cont?d) 11.5.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) be- tween the internal bus and the received shift regis- ter (see figure 53 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scierpr registers. ? set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: ? the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. ? the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the spi han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the rdr register as long as the rdrf bit is not cleared. when a overrun error occurs: ? the or bit is set. ? the rdr content will not be lost. ? the shift register will be overwritten. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr reg- ister followed by a scidr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag getting set during start bit reception, there should be a valid edge de- tection as well as three valid samples. when noise is detected in a frame: ? the nf flag is set at the rising edge of the rdrf bit. ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read op- eration followed by a scidr register read opera- tion. during reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this frame and the nf flag is set internally (not accessible to the user). this nf flag is accessible along with the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the applica- tion software when the first valid byte is received. see also section 11.5.4.10 . st72260gx, st72262gx, st72264gx 92/172 serial communications interface (cont?d) figure 55. sci baud rate and extended prescaler block diagram transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register st72260gx, st72262gx, st72264gx 93/172 serial communications interface (cont?d) framing error a framing error is detected when: ? the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. ? a break is received. when the framing error is detected: ? the fe bit is set by hardware ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read oper- ation followed by a scidr register read operation. 11.5.4.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 11.5.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry stan dard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 55 . the output clock rate sent to the transmitter or to the receiver will be the ou tput from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by set- ting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255 (see scietpr register) erpr = 1,.. 255 (see scierpr register) 11.5.4.6 receiver muting and wake-up feature in multiprocessor configurat ions it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interr upts are inhibited. a muted receiver may be awakened by one of the following two ways: ? by idle line detection if the wake bit is reset, ? by address mark detectio n if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution : in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu=1) and a address mark wake up event occurs (rwu is reset) before the write operation, the rwu bit will be set again by this write operation. consequently the address byte is lost and the sci is not woken up from mute mode. tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu st72260gx, st72262gx, st72264gx 94/172 serial communications interface (cont?d) 11.5.4.7 parity control parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in table 18 . table 18. frame formats legend: sb = start bit, stb = stop bit, pb = parity bit note : in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit even parity: the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the in- terface checks if the received data byte has an even number of ?1s? if even parity is selected (ps=0) or an odd number of ?1s? if odd parity is se- lected (ps=1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is gen- erated if pie is set in the scicr1 register. 11.5.4.8 sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detec- tion, all the three samples should have the same value otherwise the noise flag (nf) is set. for ex- ample: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be ?1?, but the noise flag bit is be set because the three samples values are not the same. consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the de- sired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. note: the internal sampling clock of the microcon- troller samples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th samples will be at 28s, 32s & 36s respectively (the first sample starting ideally at 0s). but if the falling edge of the internal clock oc- curs just before the pin value changes, the sam- ples would then be out of sync by ~4us. this means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchroniza- tion with the internal sampling clock). m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb | st72260gx, st72262gx, st72264gx 95/172 serial communications interface (cont?d) 11.5.4.9 clock deviation causes the causes which contribute to the total deviation are: ?d tra : deviation due to transmitter error (local oscillator error of the tr ansmitter or the trans- mitter is transmitting at a different baud rate). ?d quant : error due to the baud rate quantisa- tion of the receiver. ?d rec : deviation of the lo cal oscillator of the receiver: this deviation can occur during the reception of one complete sci message as- suming that the deviation has been compen- sated at the beginning of the message. ?d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% 11.5.4.10 noise error causes see also description of noise error in section 11.5.4.3 . start bit the noise flag (nf) is set during start bit reception if one of the following conditions occurs: 1. a valid falling edge is not detected. a falling edge is considered to be valid if the 3 consecu- tive samples before t he falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. 2. during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag getting set. data bits the noise flag (nf) is set during normal data bit re- ception if the following condition occurs: ? during the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag getting set. figure 56. bit sampling in reception mode rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 st72260gx, st72262gx, st72264gx 96/172 serial communications interface (cont?d) 11.5.5 low power modes 11.5.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corre- sponding enable control bi t is set and the inter- rupt mask in the cc regist er is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmit- ting/receiving until halt mode is exit- ed. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission com- plete tc tcie yes no received data ready to be read rdrf rie yes no overrun error detected or yes no idle line detected idle ilie yes no parity error pe pie yes no st72260gx, st72262gx, st72264gx 97/172 serial communications interface (cont?d) 11.5.7 register description status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register fol- lowed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data will not be transfer red to the shift reg- ister unless the tdre bit is cleared. bit 6 = tc transmission complete. this bit is set by hardwar e when transmission of a frame containing data is complete. an interrupt is generated if tcie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a pre- amble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift re gister will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be tr ansferred and only the or bit will be set. bit 0 = pe parity error. this bit is set by hardware when a parity error oc- curs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an inter- rupt is generated if pie=1 in the scicr1 register. 0: no parity error 1: parity error 70 tdre tc rdrf idle or nf fe pe st72260gx, st72262gx, st72264gx 98/172 serial communications interface (cont?d) control register 1 (scicr1) read/write reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte trans- fer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note : the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2 = pce parity control enable. this bit selects the hardware parity control (gener- ation and detection). when the parity control is en- abled, the computed parity is inserted at the msb position (9th bit if m=1; 8th bit if m=0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmis- sion). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected afte r the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hard- ware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled. 70 r8 t8 scid m wake pce ps pie st72260gx, st72262gx, st72264gx 99/172 serial communications interface (cont?d) control register 2 (scicr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the scisr register bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: ? during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. ? when te is set there is a 1 bit-time delay before the transmission starts. caution: the tdo pin is free for general purpose i/o only when the te and re bits are both cleared (or if te is never set). bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (setting the rwu bit), the sci must receive some data first, otherwise it cannot function in mute mode with wakeup by idle line detection. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter will send a break word at the end of the current word. 70 tie tcie rie ilie te re rwu sbk st72260gx, st72262gx, st72264gx 100/172 serial communications interface (cont?d) data register (scidr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 53 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 53 ). baud rate register (scibrr) read/write reset value: 0000 0000 (00h) bits 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate cl ock in conventional baud rate generator mode. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 scr1 scr0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 st72260gx, st72262gx, st72264gx 101/172 serial communications interface (cont?d) extended receive prescaler division register (scierpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bits 7:0 = erpr[7:0] 8-bit extended receive prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 55 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (scietpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bits 7:0 = etpr[7:0] 8-bit extended transmit prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 55 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. table 19. baudrate selection 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr)=128, pr=13 tr (or rr)= 32, pr=13 tr (or rr)= 16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 16, pr= 3 tr (or rr)= 2, pr=13 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr)= 1, pr=1 14400 ~14285.71 st72260gx, st72262gx, st72264gx 102/172 serial communications interface ( cont?d ) table 20. sci register map and reset values address (hex.) register name 76543210 50 scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 51 scidr reset value dr7 x dr6 x dr5 x dr4 x dr3 x dr2 x dr1 x dr0 x 52 scibrr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 53 scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 54 scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 55 scierpr reset value erpr7 0 erpr6 0 erpr5 0 erpr4 0 erpr3 0 erpr2 0 erpr1 0 erpr0 0 56 scietpr reset value etpr7 0 etpr6 0 etpr5 0 etpr4 0 etpr3 0 etpr2 0 etpr1 0 etpr0 0 st72260gx, st72262gx, st72264gx 103/172 11.6 i 2 c bus interface (i2c) 11.6.1 introduction the i 2 c bus interface serves as an interface be- tween the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, pro- tocol, arbitration and timing. it supports fast i 2 c mode (400khz). 11.6.2 main features parallel-bus/i 2 c protocol converter multi-master capability 7-bit/10-bit addressing smbus v1.1 compliant transmitter/receiver flag end-of-byte transmission flag transfer problem detection i 2 c master features: clock generation i 2 c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag start bit detection flag start and stop generation i 2 c slave features: stop bit detection i 2 c bus busy flag detection of misplaced start or stop condition programmable i 2 c address detection transfer problem detection end-of-byte transmission flag transmitter/receiver flag 11.6.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selectio n is made by soft- ware. mode selection the interface can operate in the four following modes: ? slave transmitter/receiver ? master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master ca- pability. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recog- nising its own address (7 or 10-bit), and the gen- eral call address. the ge neral call address de- tection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start con- dition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to fig- ure 57 . figure 57. i 2 c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b st72260gx, st72262gx, st72264gx 104/172 i 2 c bus interface (cont?d) acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call ad- dress can be selected by software. the speed of the i 2 c interface may be selected between standard (up to 100khz) and fast i 2 c (up to 400khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i 2 c bus mode. when the i 2 c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 58. i 2 c interface block diagram data register (dr) data shift register comparator own address register 1 (oar1) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) interrupt clock control data control scl or scli sda or sdai own address register 2 (oar2) st72260gx, st72262gx, st72264gx 105/172 i 2 c bus interface (cont?d) 11.6.4 functional description refer to the cr, sr1 and sr2 registers in section 11.6.7 . for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. 11.6.4.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set. address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in se- quence: ? acknowledge pulse if the ack bit is set. ? evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister, holding the scl line low (see figure 59 transfer sequencing ev1). next, in 7-bit mode read the dr register to deter- mine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address se- quence the slave is always in receive mode. it will enter transmit mode on receiving a repeated start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the inter- nal shift register. after each byte the interface gen- erates in sequence: ? acknowledge pulse if the ack bit is set ? evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 59 transfer se- quencing ev2). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 59 transfer sequencing ev3). when the acknowledge pulse is received: ? the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop con- dition is generated by the master. the interface detects this condition and sets: ? evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 reg- ister (see figure 59 transfer sequencing ev4). error cases ? berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. ? af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an inter- rupt if the ite bit is set. the af bit is cleared by reading the i2csr2 reg- ister. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. soft- ware must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. note : in case of errors, sc l line is not held low; however, the sda line can remain low if the last bits transmitted are all 0. while af=1, the scl line may be held low due to sb or btf flags that are set at the same time. it is then necessary to re- lease both lines by software. st72260gx, st72262gx, st72264gx 106/172 i 2 c interface (cont?d) how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. smbus compatibility st7 i 2 c is compatible with sm bus v1.1 protocol. it supports all smbus adressing modes, smbus bus protocols and crc-8 packet error checking. refer to an1713: smbus slave driver for st7 i 2 c pe- ripheral. 11.6.4.2 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condi- tion. once the start condition is sent: ? the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register with the slave address, holding the scl line low (see figure 59 transfer sequencing ev5). slave address transmission then the slave address is sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the follow- ing event: ? the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register, holding the scl line low (see figure 59 transfer se- quencing ev9). then the second address byte is sent by the inter- face. after completion of this transfer (and acknowledge from the slave if the ack bit is set): ? the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the cr register (for exam- ple set pe bit), holding the scl line low (see fig- ure 59 transfer sequencing ev6). next the master must enter receiver or transmit- ter mode. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr reg- ister via the internal shift register. after each byte the interface generates in sequence: ? acknowledge pulse if the ack bit is set ? evf and btf bits are set by hardware with an in- terrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 59 transfer se- quencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. st72260gx, st72262gx, st72264gx 107/172 i 2 c bus interface (cont?d) master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the inter- nal shift register. the master waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 59 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: ? evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to gener- ate the stop condition. the interface goes auto- matically back to slave mode (m/sl bit cleared). error cases ? berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if ite is set. note that berr will not be set if an error is de- tected during the first or second pulse of each 9- bit transaction: single master mode if a start or stop is issued during the first or sec- ond pulse of a 9-bit transaction, the berr flag will not be set and trans fer will continue however the busy flag will be reset. to work around this, slave devices should issue a nack when they receive a misplaced start or stop. the reception of a nack or busy by the master in the middle of communication gives th e possibility to reiniti- ate transmission. multimaster mode normally the berr bit would be set whenever unauthorized transmission takes place while transfer is already in progress. however, an is- sue will arise if an external master gen erates an unauthorized start or stop while the i 2 c master is on the first or second pulse of a 9-bit transac- tion. it is possible to wo rk around this by polling the busy bit during i 2 c master mode transmis- sion. the resetting of the busy bit can then be handled in a similar manner as the berr flag being set. ? af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. the af bit is cleared by reading the i2csr2 reg- ister. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. soft- ware must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. ? arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note : in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ?0? bits transmitted last. it is then neces- sary to release both lines by software. st72260gx, st72262gx, st72264gx 108/172 i 2 c bus interface (cont?d) figure 59. transfer sequencing legend: s=start, s r = repeated start, p=stop, a=ac knowledge, na=non-acknowledge, evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading sr1 register. ev2: evf=1, btf=1, cleared by reading sr1 regi ster followed by reading dr register. ev3: evf=1, btf=1, cleared by reading sr1 regi ster followed by writing dr register. ev3-1: evf=1, af=1, btf=1; af is cl eared by reading sr1 register. btf is cleared by releasing the lines (stop=1, stop=0) or by writing dr register (dr=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading sr2 register. ev5: evf=1, sb=1, cleared by reading sr1 register followed by writing dr register. ev6: evf=1, cleared by reading sr1 register follow ed by writing cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading sr1 regi ster followed by reading dr register. ev8: evf=1, btf=1, cleared by reading sr1 regi ster followed by writing dr register. ev9: evf=1, add10=1, cleared by reading sr1 register followed by writing dr register. 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter 10-bit master receiver: s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a .... . datan a p ev1 ev3 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7 st72260gx, st72262gx, st72264gx 109/172 i 2 c bus interface (cont?d) 11.6.5 low power modes 11.6.6 interrupts figure 60. event flags and interrupt generation note : the i 2 c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc reg- ister is reset (rim instruction). mode description wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an in terrupt with ?exit from halt mode? capability. interrupt event event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite yes no end of byte transfer event btf yes no address matched event (slave mode) adsel yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multima ster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register. add10 st72260gx, st72262gx, st72264gx 110/172 i 2 c bus interface (cont?d) 11.6.7 register description i 2 c control register (cr) read / write reset value: 0000 0000 (00h) bit 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability notes: ? when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 ? when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. ? to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). the 00h general call address is ac- knowledged (01h ignored). 0: general call disabled 1: general call enabled note: in accordance with the i2c standard, when gcal addressing is enabl ed, an i2c slave can only receive data. it will not transmit data to the master. bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). ? in master mode: 0: no start generation 1: repeated start generation ? in slave mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). ? in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. ? in slave mode: 0: no stop generation 1: release the scl and sda lines after the cur- rent byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 60 for the relationship between the events and the interrupt. scl is held low when the add10, sb, btf or adsl flags or an ev6 event (see figure 59 ) is de- tected. 70 0 0 pe engc start ack stop ite st72260gx, st72262gx, st72264gx 111/172 i 2 c bus interface (cont?d) i 2 c status register 1 (sr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event oc- curs. it is cleared by software reading sr2 register in case of error event or as described in figure 59 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: ? btf=1 (byte received or transmitted) ? adsl=1 (address matched in slave mode while ack=1) ? sb=1 (start condition generated in master mode) ? af=1 (no acknowledge received after byte transmission) ? stopf=1 (stop condition detected in slave mode) ? arlo=1 (arbitration lost in master mode) ? berr=1 (bus error, misplaced start or stop condition detected) ? add10=1 (master has sent header byte) ? address byte successfully transmitted in mas- ter mode. bit 6 = add10 10-bit addressing in master mode . this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading sr2 register followed by a write in the dr register of the second address byte. it is also cleared by hardware when the pe- ripheral is disabled (pe=0). 0: no add10 event occurred. 1: master has sent first address byte (header) bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after de- tection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disa- bled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. the busy flag of the i2csr1 register is cleared if a bus error occurs. 0: no communication on the bus 1: communication ongoing on the bus note: ? the busy flag is not updated when the inter- face is disabled (pe=0) . this can have conse- quences when operating in multimaster mode; i.e. a second active i 2 c master commencing a transfer with an unset busy bit can cause a con- flict resulting in lost dat a. a software workaround consists of checking that the i 2 c is not busy be- fore enabling the i 2 c multimaster cell. bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr reg- ister. it is also cleared by hardware when the inter- face is disabled (pe=0). ? following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 59 ). btf is cleared by reading sr1 register followed by writ- ing the next byte in dr register. ? following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register con- tent or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software read- ing sr1 register or by hardware when the inter- face is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched 70 evf add10 tra busy btf adsl m/sl sb st72260gx, st72262gx, st72264gx 112/172 i 2 c bus interface (cont?d) bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no start condition 1: start condition generated i 2 c status register 2 (sr2) read only reset value: 0000 0000 (00h) bit 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interfac e is disabled (pe=0). the scl line is not held low while af=1 but by oth- er flags (sb or btf) that are set at the same time. 0: no acknowledge failure 1: acknowledge failure note: ? when an af event occurs, the scl line is not held low; however, the sda line can remain low if the last bits transmitted are all 0. it is then nec- essary to release both lines by software. bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interfac e is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost . this bit is set by hardwa re when the interface los- es the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by soft- ware reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected note: ? in a multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the acknowledge bit. mishandling of the arlo bit from the i2csr2 register may occur when a sec- ond master simultaneou sly requests the same data from the same slave and the i 2 c master does not acknowledge the data. the arlo bit is then left at 0 instead of being set. bit 1 = berr bus error. this bit is set by hardware when the interface de- tects a misplaced start or stop condition. an inter- rupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the in- terface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition note: ? if a bus error occurs, a stop or a repeated start condition should be generated by the master to re-synchronize communication, get the transmis- sion acknowledged and the bus released for fur- ther communication bit 0 = gcal general call (slave mode). this bit is set by hardwa re when a general call ad- dress is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 70 0 0 0 af stopf arlo berr gcal st72260gx, st72262gx, st72264gx 113/172 i 2 c bus interface (cont?d) i 2 c clock control register (ccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bit 6:0 = cc[6:0] 7-bit clock divider. these bits select the speed of the bus (f scl ) de- pending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). refer to the electrical characteristics section for the table of values. note: the programmed f scl assumes no load on scl and sda lines. i 2 c data register ( dr) read / write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] 8-bit data register. these bits contain the byte to be received or trans- mitted on the bus. ? transmitter mode: byte transmission start auto- matically when the software writes in the dr reg- ister. ? receiver mode: the first data byte is received au- tomatically in the dr register using the least sig- nificant bit of the address. then, the following data bytes are received one by one after reading the dr register. 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 d7 d6 d5 d4 d3 d2 d1 d0 st72260gx, st72262gx, st72264gx 114/172 i 2 c bus interface (cont?d) i 2 c own address register (oar1) read / write reset value: 0000 0000 (00h) 7-bit addressing mode bit 7:1 = add[7:1] interface address . these bits define the i 2 c bus address of the inter- face. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is don?t care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 10-bit addressing mode bit 7:0 = add[7:0] interface address . these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). i 2 c own address register (oar2) read / write reset value: 0100 0000 (40h) bit 7:6 = fr[1:0] frequency bits. these bits are set by software only when the inter- face is disabled (pe=0). to configure the interface to i 2 c specified delays select the value corre- sponding to the microcontroller frequency f cpu . bit 5:3 = reserved bit 2:1 = add[9:8] interface address . these are the most significant bits of the i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe=0). bit 0 = reserved. 70 add7 add6 add5 add4 add3 add2 add1 add0 70 fr1 fr0 0 0 0 add9 add8 0 f cpu fr1 fr0 < 6 mhz 0 0 6 to 8 mhz 0 1 st72260gx, st72262gx, st72264gx 115/172 i2c bus interface (cont?d) table 21. i 2 c register map and reset values address (hex.) register label 76543210 0028h i2ccr reset value 0 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 0029h i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 002ah i2csr2 reset value000 af 0 stopf 0 arlo 0 berr 0 gcal 0 02bh i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 02ch i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 002dh i2coar2 reset value fr1 0 fr0 1000 add9 0 add8 00 002eh i2cdr reset value msb 0000000 lsb 0 st72260gx, st72262gx, st72264gx 116/172 11.7 10-bit a/d converter (adc) 11.7.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has 6 multiplexed analog input chan- nels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from 6 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 11.7.2 main features 10-bit conversion 6 channels with multiplexed input linear successive approximation data register (dr) which contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 61 . 11.7.3 functional description 11.7.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 61. adc block diagram ch2 ch1 eoc speed adon slow ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 3 f adc f cpu d1 d0 adcdrl 00 0000 0 f cpu, f cpu /2 , f cpu /4 st72260gx, st72262gx, st72264gx 117/172 10-bit a/d converter (adc) (cont?d) 11.7.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the a dcdrh register and 03h in the adcdrl register (with out overflow indication). if the input voltage (v ain ) is lower than v ssa (low- level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrh and ad- cdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.7.3.3 a/d conversion the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: ? select the ch[2:0] bits to assign the analog channel to convert. adc conversion mode in the adccsr register: - set the speed or the slow bits ? set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? the result is in the adcdr registers. a read to the adcdrh or a write to any bit of the adccsr resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll eoc bit 2. read adcdrl. this locks the adcdrh until it is read. 3. read adcdrh. this clears eoc automati- cally. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this clears eoc automati- cally. 11.7.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed and between single shot conversions. 11.7.5 interrupts none. mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. st72260gx, st72262gx, st72264gx 118/172 10-bit a/d converter (adc) (cont?d) 11.7.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by soft- ware reading the adcdrh register or writing to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete bit 6 = speed a/d clock selection this bit is set and cleared by software. table 22. a/d clock selection (see note 1) 1) the speed and slow bits must be updated before setting the adon bit. 2) use this setting only if f cpu 4 mhz bit 5 = adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion bit 4 = slow a/d clock selection this bit is set and cleared by software. it works to- gether with the speed bit. refer to table 22 . bit 2:0 = ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. data register (adcdrh) read only reset value: 0000 0000 (00h) bit 7:0 = d[9:2] msb of analog converted value data register (adcdrl) read only reset value: 0000 0000 (00h) bit 7:2 = reserved. forced by hardware to 0. bit 1:0 = d[1:0] lsb of analog converted value 70 eoc speed adon slow 0 ch2 ch1 ch0 f adc frequency slow speed f cpu (see note 2) 0 1 f cpu /2 11 00 f cpu /4 1 0 channel pin ch2 ch1 ch0 ain0 000 ain1 001 ain2 010 ain3 011 ain4 100 ain5 101 70 d9 d8 d7 d6 d5 d4 d3 d2 70 000000d1d0 st72260gx, st72262gx, st72264gx 119/172 10-bit a/d converter (adc) (cont?d) table 23. adc register map and reset values address (hex.) register label 76543210 006fh adcdrl reset value 000000 d1 0 d0 0 0070h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0071h adccsr reset value eoc 0 speed 0 adon 0 slow 00 ch2 0 ch1 0 ch0 0 st72260gx, st72262gx, st72264gx 120/172 12 instruction set 12.1 cpu addressing modes the cpu features 17 different addressing modes which can be classified in 7 main groups: the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: ? long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 24. cpu addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([ $10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10. w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],# 7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10] ,#7,skip 00..ff 00..ff byte + 3 st72260gx, st72262gx, st72264gx 121/172 instruction set overview (cont?d) 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 12.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, t hus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations st72260gx, st72262gx, st72264gx 122/172 instruction set overview (cont?d) 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 25. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative st72260gx, st72262gx, st72264gx 123/172 instruction set overview (cont?d) 12.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 ma in groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. 12.2.1 illegal opcode reset in order to provide enhanced robustness to the de- vice against unexpected behaviour, a system of il- legal opcode detection is implemented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, com- bined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf st72260gx, st72262gx, st72264gx 124/172 instruction set overview (cont?d) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. int pin = 1 (ext. int pin high) jril jump if ext. int pin = 0 (ext. int pin low) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > st72260gx, st72262gx, st72264gx 125/172 instruction set overview (cont?d) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z st72260gx, st72262gx, st72264gx 126/172 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v (for the 3v v dd 5.5v volt- age range) and v dd =2.7v (for the 2.7v v dd 3v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 62 . figure 62. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 63 . figure 63. pin input voltage c l st7 pin v in st7 pin st72260gx, st72262gx, st72264gx 127/172 13.2 absolute ma ximum ratings stresses above those listed as ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 13.2.1 voltage characteristics 13.2.2 current characteristics 13.2.3 thermal characteristics notes: 1. directly connecting the i/o pins to v dd or v ss could damage the device if an unexpec ted change of the i/o configura- tion occurs (for example, due to a co rrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-dow n resistor (typical: 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configurat ion. for reset pin, please refer to figure 91 and figure 92 . 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72260gx, st72262gx, st72264gx 129/172 operating conditions (cont?d) 13.3.2 operating c onditions with l ow voltage detector (lvd) t a = -40 to +85c unless otherwise specified notes: 1. data based on characterization results, not tested in production. 2. when vt por is faster than 100 s/v, the reset signal is released af ter a delay of max. 42s after v dd crosses the v it+(lvd) threshold. 3. use of lvd with capacitive power supply: with this type of power supply, if power cuts occu r in the application, it is recommended to pull v dd down to 0v to ensure optimum restart conditions. refer to circuit example in figure 91 on page 151 and note 6. . figure 65. lvd startup behaviour note: when the lvd is enabled, the mcu reaches its authorized operating voltage from a reset state. however, in some devices, the reset signal may be undefined until v dd is approximately 2v. as a conse- quence, the i/os may toggle when v dd is below this voltage. because flash write access is impossible below this voltage, the flash memory contents will not be cor- rupted. symbol parameter conditions min typ max unit v it+(lvd) reset release threshold (v dd rise) high threshold med. threshold low threshold 4.0 1) 3.55 1) 2.95 1) 4.2 3.75 3.15 4.5 4.0 3.35 v v it-(lvd) reset generation threshold (v dd fall) high threshold med. threshold low threshold 3.75 3.3 2.75 4.0 3.55 3.0 4.25 1) 3.75 1) 3.15 1) v hys(lvd) lvd voltage threshold hysteresis v it+(lvd) -v it-(lvd) 200 mv vt por v dd rise time rate 1)2)3) flash 20 s/v 20ms/v rom 20 s/v t g(vdd) filtered glitch delay on v dd 1) not detected by the lvd 40 ns 5v 2v v it+ lvd reset v d d t reset state in this area not defined st72260gx, st72262gx, st72264gx 130/172 operating conditions (cont?d) 13.3.3 auxiliary voltage detector (avd) thresholds t a = -40 to +85c unless otherwise specified 1. data based on characterization results, not tested in production. symbol parameter conditions min typ max unit v it+(avd) 1 ? 0 avdf flag toggle threshold (v dd rise) vd level = low in option byte vd level = med. in option byte vd level = high in option byte 4.4 1) 3.9 1) 3.4 1) 4.6 4.2 3.6 4.9 4.4 3.8 v v it-(avd) 0 ? 1 avdf flag toggle threshold (v dd fall) vd level = low in option byte vd level = med. in option byte vd level = high in option byte 4.15 3.75 3.1 4.4 3.95 3.4 4.65 1) 4.2 1) 3.6 1) v hys(avd) avd voltage threshold hysteresis v it+(avd) -v it-(avd) 250 mv ? v it- voltage drop between avd flag set and lvd reset activated v it-(avd) -v it-(lvd) 450 st72260gx, st72262gx, st72264gx 131/172 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consump- tion, the two current values must be added (except for halt mode for which the clock is stopped). 13.4.1 run, slow, wait and slow wait modes t a = -40 to +85c unless otherwise specified notes: 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. program executed from ram, cpu running with memory acce ss, all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, lvd disabled. 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in re set state; clock input (osc1) driven by external square wave, lvd disabled. 4. data based on characterization results, not tested in production. symbol parameter conditions max unit ? i dd( ? ta) supply current variation vs. temperature constant v dd and f cpu 10 % symbol parameter conditions flash rom unit typ max typ max unit i dd supply current in run mode 2) (see figure 66 ) v dd =5.5v,f osc =16mhz, f cpu =8mhz v dd =2.7v, f osc =8mhz, f cpu =4mhz 7.2 3.5 11 1) 5.25 4) 5.0 1.2 tbd ma supply current in slow mode 3) (see figure 67 ) v dd =5.5v, f osc =16mhz, f cpu =500khz v dd =2.7v, f osc =8mhz, f cpu =250khz 0.7 0.38 1.2 1) 0.6 4) 0.5 0.13 tbd supply current in wait mode 2) (see figure 68 ) v dd =5.5v,f osc =16mhz, f cpu =8mhz v dd =2.7v, f osc =8mhz, f cpu =4mhz 3.6 1.8 5.55 1) 3 4) 2.3 0.5 tbd supply current in slow wait mode 3) (see figure 69 ) v dd =5.5v, f osc =16mhz, f cpu =500khz v dd =2.7v, f osc =8mhz, f cpu =250khz 0.45 0.25 1 1) 0.5 4) 0.33 0.08 tbd st72260gx, st72262gx, st72264gx 132/172 supply current characteristics (cont?d) figure 66. typical i dd in run at t a =25c figure 67. typical i dd in slow at t a =25c figure 68. typical i dd in wait at t a =25c figure 69. typ. i dd in slow-wait at t a =25c 0 1 2 3 4 5 6 7 8 9 10 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd (ma) fosc=16mhz fosc=8mhz fosc=4mhz fosc=2mhz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2.533.544.555.566.5 vdd(v) idd(ma) fosc=16mhz fosc=8mhz fosc=4mhz fosc=2mhz 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2.533.544.555.566.5 vdd(v) idd(ma) fosc=16mhz fosc=8mhz fosc=4mhz fosc=2mhz 0 0.1 0.2 0.3 0.4 0.5 0.6 2.533.544.555.566.5 vdd(v) idd(ma) fosc=16mhz fosc=8mhz fosc=4mhz fosc=2mhz st72260gx, st72262gx, st72264gx 133/172 supply current characteristics (cont?d) 13.4.2 halt and active-halt modes 13.4.3 supply and clock managers the previous current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode). notes: 1. all i/o pins in output m ode with a static value at v ss (no load), lvd disabl ed. data based on characterization results, tested in production at v dd max. and f cpu max. 2. data based on characterisation results, not tested in production. all i/o pins in output mode wi th a static value at v ss (no load); clock input (osc1) driven by external square wave, lvd disabled. to obtain the total current consumption of the device, add the clock source consumption ( section 13.5.3 and section 13.5.4 ). 3. data based on characterization results done wi th the external components specified in section 13.5.3 and section 13.5.4 , not tested in production. 4. as the oscillator is based on a current sour ce, the consumption does not depend on the voltage. symbol parameter conditions typ max unit i dd supply current in halt mode 1) v dd =5.5v -40c t a +85c <1 10 a v dd =2.7v -40c t a +85c <1 6 supply current in active-halt mode 2) 500 no max. guaran- teed symbol parameter conditions typ max unit i dd(rcint) supply current of inte rnal rc oscillator 900 a i dd(res) supply current of re sonator oscillator 3) & 4) see section 13.5.3 on page 136 i dd(pll) pll supply current v dd =5v 100 i dd(lvd) lvd supply current halt mode 100 st72260gx, st72262gx, st72264gx 134/172 supply current characteristics (cont?d) 13.4.4 on-chip peripherals notes: 1. data based on a differential i dd measurement between reset configur ation (timer count er running at f cpu /2) and timer counter stopped (only ti md bit set). data valid for one timer. 2. data based on a differential i dd measurement between reset configuration (spi disabled) and a permanent spi master communication at maximum speed (data sent equal to ffh).this measurement includes the pad toggling consumption. 3. data based on a differential i dd measurement between sci running at ma ximum speed configurat ion (500 kbaud, con- tinuous transmission of aa +re enabled and sci off. this measurement includes the pad toggling consumption. 4. data based on a differential i dd measurement between reset c onfiguration (i2c disabled) and a permanent i2c master communication at 300khz (data sent equal to aah). th is measurement includes t he pad toggling consumption (4.7kohm external pull- up on clock and data lines). 5. data based on a differential i dd measurement between reset configurati on (adc off) and conti nuous a/d conversion (f adc =4mhz). symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current 1) f cpu =4mhz v dd = 3.0v 200 a f cpu =8mhz v dd = 5.0v 300 i dd(spi) spi supply current 2) f cpu =4mhz v dd = 3.0v 200 f cpu =8mhz v dd = 5.0v 250 i dd(sci) sci supply current 3) f cpu =4mhz v dd = 3.0v 350 f cpu =8mhz v dd = 5.0v 650 i dd(i2c) i2c supply current 4) f cpu =4mhz v dd = 3.0v 350 f cpu =8mhz v dd = 5.0v 500 i dd(adc) adc supply current when converting 5) f adc =4mhz v dd = 3.0v 500 v dd = 5.0v 600 st72260gx, st72262gx, st72264gx 135/172 13.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . 13.5.1 general timings 13.5.2 external clock source figure 70. typical application with an external clock source notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to finish the current instru ction execution. 3. data based on design simulation and/or technol ogy characteristics, not tested in production. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2312t cpu f cpu =8mhz 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = ? t c(inst) + 10 10 22 t cpu f cpu =8mhz 1.25 2.75 s symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 70 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 3) 15 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 i l oscx input leakage current v ss v in v dd 1 a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% st72260gx, st72262gx, st72264gx 136/172 clock and timing characteristics (cont?d) 13.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the reso- nator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distorti on and start-up stabiliza- tion time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, pack- age, accuracy...). figure 71. typical application with a crystal or ceramic resonator notes: 1. the oscillator selection can be opt imized in terms of supply current usi ng an high quality resonat or with small r s value. refer to crystal/ceramic resonator manufacturer for more details. symbol parameter conditions min max unit f osc oscillator frequency 1) vlp : very low power oscillator lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 0.032 1 >2 >4 >8 0.1 2 4 8 16 mhz r f feedback resistor 20 40 k ? c l1 c l2 recommended load capacitance ver- sus equivalent serial resistance of the crystal or ceramic resonator (r s ) vlp oscillator r s =200 ? lp oscillator r s =200 ? mp oscillator r s =200 ? ms oscillator r s =100 ? hs oscillator 60 38 32 10 10 100 100 47 47 30 pf symbol parameter conditions typ max unit i 2 osc2 driving current vlp oscillator v dd =5v lp oscillator v in =v ss mp oscillator ms oscillator hs oscillator 2.5 80 160 310 610 5 150 250 460 900 a osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors r d st72260gx, st72262gx, st72264gx 137/172 clock and timing characteristics (cont?d) notes: 1. resonator characteristics given by the ceramic resonator manufacturer. 2. smd = [-r0: plastic tape package ( ? =180mm), -b0: bulk] lead = [-a0: flat pack package (radi al taping ho= 18mm), -b0: bulk] 3. lp mode is not recommended for 2 mhz resonator bec ause the peak to peak amplitude is too small (>0.8v) for more information on these resonat ors, please consult www.murata.com supplier f osc (mhz) typical ceramic resonators reference 2) recommended oscrnge option bit configuration murata 2 cstcc2m00g56a-r0 mp mode 3) 4 cstcr4m00g55b-r0 ms mode 8 cstce8m00g55a-r0 hs mode 16 cstce16m0g53a-r0 hs mode st72260gx, st72262gx, st72264gx 138/172 clock characteristics (cont?d) 13.5.4 rc oscillators the st7 internal clock can be supplied with an in- ternal rc oscillator. figure 72. typical application with rc oscillator figure 73. typical f osc(rcint) vs v dd symbol parameter conditions min typ max unit f osc (rcint) internal rc oscillator frequency see figure 73 t a =25c, v dd =5v 23.5 6mhz f osc internal rc v ref + - v dd current copy voltage generator c ex discharge st72xxx r in c in 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2.35 5 5.5 vdd(v ) f(mhz) t= 25c t=130c t=-45c st72260gx, st72262gx, st72264gx 139/172 clock characteristics (cont?d) 13.5.5 pll characteristics note: 1. data characterized but not tested. figure 74. pll jitter vs. signal frequency 1 the user must take the pll jitter into account in the application (for example in serial communica- tion or sampling of high frequency signals). the pll jitter is a periodic e ffect, which is integrated over several cpu cycles. therefore the longer the period of the application signal, the less it will be impacted by the pll jitter. figure 74 shows the pll jitter integrated on appli- cation signals in the range 125khz to 2mhz. at fre- quencies of less than 125khz, the jitter is negligi- ble. note 1: measurement conditions: f cpu = 4mhz, t a = 25c symbol parameter conditions min typ max unit v dd(pll) pll operating range t a 0 to 70 c 3.5 5.5 v t a -40 to +85 c 4.5 5.5 f osc pll input frequency range 2 4 mhz ? f cpu /f cpu instantaneous pll jitter 1) f osc = 4 mhz. 1.0 2.5 % f osc = 2 mhz. 2.5 4.0 % 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2000 1000 500 250 125 application signal frequency (khz) +/-jitter (%) pll on pll off st72260gx, st72262gx, st72264gx 140/172 13.6 memory characteristics 13.6.1 ram and hardware registers 13.6.2 xflash program memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). guaranteed by construction, not tested in production. 2. up to 32 bytes can be programmed at a time. 3. the data retention time increases when the t a decreases. 4. data based on reliability test results and monitored in production. 5. data based on characterization results, not tested in production. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit v dd operating voltage for flash write/ erase 2.7 5.5 v t prog programming time for 1~32 bytes 2) t a =? 40 to +85c 5 10 ms programming time for 1.5kbytes t a = +25c 0.24 0.48 t ret data retention 4) t a = +55c 3) 20 years n rw write erase cycles t a = +25c 10 kcycles i dd supply current read / write / erase modes f cpu = 8mhz, v dd = 5.5v 2.6 3) ma no read/no write mode 100 a power down mode / halt 0 0.1 5) a st72260gx, st72262gx, st72264gx 141/172 13.7 emc characteristics susceptibility tests are pe rformed on a sample ba- sis during product characterization. 13.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test confor ms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. the test results are given in the table be- low based on the ems levels and classes defined in application note an1709. 13.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). figure 75. emc recommended power supply connection 1) 1. the suggested 10 f and 0.1 f decoupling capacitors on the power supply lines are proposed as a good price vs. emc performance tradeoff. they have to be put as close as po ssible to the device power supply pins. other emc recommen- dations are given in an1709. symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 2b v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v dd pins to induce a func- tional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 2b v dd v ss 0.1 f 10 f v dd st72xxx power supply source st7 digital noise filtering st72260gx, st72262gx, st72264gx 142/172 emc characteristics (cont?d) 13.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/ 3 which specifies the board and the loading of each pin. 13.7.3 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measuremen t methods, the product is stressed in order to determine its performance in terms of electrical sensitiv ity. for more details, re- fer to the application note an1181. 13.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test con- forms to the jesd22-a114a/a115a standard. absolute maximum ratings notes: 1. data based on characterization results, not tested in production. symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 8/4mhz 16/8mhz s emi peak level v dd = 5v, t a = +25c, conforming to sae j 1752/3 0.1mhz to 30mhz 10 13 db v 30mhz to 130mhz 13 24 130mhz to 1ghz 16 31 sae emi level 2.5 4 - symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25c 200 st72260gx, st72262gx, st72264gx 143/172 emc characteristics (cont?d) 13.7.3.2 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1 000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities notes: 1. class description: a class is an stmicr oelectronics internal specif ication. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standar d. b class strictly covers all the jedec criteria (int ernational standard). symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c a a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a st72260gx, st72262gx, st72264gx 144/172 13.8 i/o port pin characteristics 13.8.1 general characteristics t a = -40 to +85c unless otherwise specified notes: 1. data based on characterization results, not tested in production. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72260gx, st72262gx, st72264gx 146/172 i/o port pin characteristics (cont?d) 13.8.2 output driving current t a = -40 to +85c unless otherwise specified notes: 1. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . 3. not tested in production, based on characterization results. symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time v dd =5v i io =+5ma 1.2 v i io =+2ma 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+20ma, 1.3 i io =+8ma 0.75 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-5ma, v dd -1.6 i io =-2ma v dd -0.8 v ol 1)3) output low level voltage for a standard i/o pin when 8 pins are sunk at same time v dd =3.3v i io =+2ma 0.6 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+8ma 0.6 v oh 2)3) output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-2ma t a 85c v dd -0.8 v ol 1)3) output low level voltage for a standard i/o pin when 8 pins are sunk at same time v dd =2.7v i io =+2ma 0.7 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+8ma 0.7 v oh 2)3) output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-2ma v dd -0.9 st72260gx, st72262gx, st72264gx 147/172 i/o port pin characteristics (cont?d) figure 80. typ. v ol at v dd =5v (standard) figure 81. typ. v ol at v dd =3v (high-sink) figure 82. typ. v ol at v dd =2.7v (standard) figure 83. typ. v ol at v dd =5v (high-sink) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 012345678910 iio(ma) vol(v) at vdd= 5v t=25c t=90c t= -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0246810121416 iol(ma) vol(v) t=25c t=90c t= -45c 0.0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 012 iio(ma) vol (v) t=25c t=90c t=-45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 01234567891011121314151617181920 iio(ma) vol(v) at vdd=5v t= 25c t= 90c t= -45c st72260gx, st72262gx, st72264gx 148/172 i/o port pin characteristics (cont?d) figure 84. typ. v oh at v dd =2.7v figure 85. typ. v oh at v dd =4v figure 86. typ. v oh at v dd =3v figure 87. typ. v oh at v dd =5v notes: 1. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . 0 0.5 1 1.5 2 2.5 3 00.511.52 iio( ma ) voh(v) t=25c t=90c t=-45c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 012345 iio( ma ) voh(v) t=25c t=90c t=-45c 0 0.5 1 1.5 2 2.5 3 3.5 0123 iio( ma ) voh(v) t=25c t=90c t=-45c 0 1 2 3 4 5 6 012345 iio( ma ) voh(v) t=25c t=90c t=-45c st72260gx, st72262gx, st72264gx 149/172 i/o port pin characteristics (cont?d) figure 88. typical v ol vs. v dd on standard i/o port (ports b and c) figure 89. typical v ol vs. v dd on high sink i/o port (port a) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 2.533.54 55.56 vdd (v) vol(v) at iio= 2ma t=25c t=90c t=-45c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 3.5 4 5 5.5 6 vdd (v) vol(v) at iio= 5ma t=25c t=90c t=-45c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 2.4 3 3.5 4 5 5.5 6 vdd (v) vol(v) at iio= 8ma t=25c t=90c t=-45c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 33.54 55.56 vdd (v) vol(v) at iio= 20ma t=25c t=90c t=-45c st72260gx, st72262gx, st72264gx 150/172 13.9 control pin characteristics 13.9.1 asynchronous reset pin t a = -40 to +85c unless otherwise specified figure 90. typical i pu on reset pin notes: 1. data based on characterization results, not tested in production. 2. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vss . 3. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3xv dd v v ih input high level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis 1) 2.5 v v ol output low level voltage 2) v dd =5v i io =+5ma 0.68 0.95 v i io =+2ma 0.28 0.45 r on pull-up equivalent resistor v dd =5v 20 40 80 k ? v dd =3v 85 t w(rstl)out generated reset pulse duratio n internal reset sources 30 s t h(rstl)in external reset pulse hold time 3) 20 s t g(rstl)in filtered glitch duration 200 ns 0 50 100 150 200 250 2.43 4 5 5.56 vdd (v) ipu(ua) at vin=vss t=25c t=90c t=-45c st72260gx, st72262gx, st72264gx 151/172 control pin characteristics (cont?d) figure 91. reset pin protection when lvd is enabled. 1)2)3)4) figure 92. reset pin protection when lvd is disabled. 1) note 1: ? the reset network protects the device against parasitic resets. ? the output of the external reset circuit must have an open- drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). ? whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.9.1 on page 150 . otherwise the reset will not be taken into account internally. ? because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must en- sure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 13.2.2 on page 127 . note 2: when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to fi lter noise on the reset line. note 3: in case a capacitive power supply is used, it is recommended to connect a 1m ? pull-down resistor to the reset pin to discharge any residual voltage induc ed by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). note 4: tips when using the lvd: ? 1. check that all recommendations related to the reset circuit have been applied (see notes above). ? 2. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m ? pull-down on the reset pin. ? 3. the capacitors connected on the reset pin and also the power supply are key to avoi d any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. otherwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor.? note 5: please refer to ?illegal opcode reset? on page 123 for more details on illegal opcode reset conditions. 0.01 f st72xxx pulse generator filter r on v dd internal reset reset external required 1m ? optional (note 3) watchdog lvd reset illegal opcode 5) 0.01 f 0.01 f v dd external reset circuit user v dd 4.7k ? required recommended for emc st72xxx pulse generator filter r on v dd internal reset watchdog illegal opcode 5) st72260gx, st72262gx, st72264gx 152/172 13.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). 13.10.1 16-bit timer t a = -40 to +85c unless otherwise specified symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu =8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 16 bit st72260gx, st72262gx, st72264gx 153/172 13.11 communication interface characteristics 13.11.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics ( ss , sck, mosi, miso). figure 93. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or charac terisation results, not tested in production. 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in st72260gx, st72262gx, st72264gx 154/172 communication interface characteristics (cont?d) figure 94. spi slave timing diagram with cpha=1 1) figure 95. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in seenote2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) st72260gx, st72262gx, st72264gx 155/172 communication interface characteristics (cont?d) 13.11.2 i 2 c - inter ic control interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). refer to table 26 for the speed conditions. the st7 i 2 c interface meets the re- quirements of the standard i 2 c communication protocol described in the following table. figure 96. typical application with i 2 c bus and timing diagram 4) notes: 1. data based on standard i 2 c protocol requirement, not tested in production. 2. the device must internally provide a hold time of at least 300ns for the sd a signal in order to bridge the undefined region of the falling edge of scl. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 4. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 5. at 4mhz f cpu , max.i 2 c speed (400khz) is not achievable. in this case, max. i 2 c speed will be approximately 260khz. symbol parameter standard mode i 2 c fast mode i 2 c 5) unit min 1) max 1) min 1) max 1) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3) 0 2) 900 3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda scl 4.7k ? sdai st72xxx scli v dd 100 ? 100 ? v dd 4.7k ? i 2 cbus st72260gx, st72262gx, st72264gx 156/172 communication interface characteristics (cont?d) the following table gives the values to be written in the i2cccr register to obtain the required i 2 c scl line frequency. table 26. scl frequency table legend: r p = external pull-up resistance f scl = i 2 c speed na = not achievable note: ? for speeds around 200 khz, achieved speed can have 5% tolerance ? for other speed ranges, achieved speed can have 2% tolerance the above variations depend on the accuracy of the external components used. f scl (khz) i2cccr value f cpu =4 mhz. f cpu =8 mhz. v dd = 3.3 v v dd = 5 v v dd = 3.3 v v dd = 5 v r p =3.3k ? r p =4.7k ? r p =3.3k ? r p =4.7k ? r p =3.3k ? r p =4.7k ? r p =3.3k ? r p =4.7k ? 400 na na na na 83h na 83h 83h 300 na na na na 85h 85h 85h 85h 200 83h 84h 83h 84h 8ah 89h 8ah 8ah 100 10h 10h 10h 10h 24h 23h 24h 23h 50 24h 24h 24h 24h 4ch 4ch 4ch 4ch 20 5fh 5fh 5fh 5fh ffh ffh ffh ffh st72260gx, st72262gx, st72264gx 157/172 13.12 10-bit adc characteristics v dd = 2.7 to 5.5v, t a = -40c to 85c, unless otherwise specified figure 97. r ain max. vs f adc with c ain =0pf 2) figure 98. recommended c ain /r ain values 3) figure 99. analog input equivalent circuit notes: 1. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k ? ). data based on characterization resu lts, not tested in production. 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad ca- pacitance (3pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 3. this graph shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization time and decreased to allow the use of a larger serial resistor (r ain) . it is valid for all f adc frequencies 4mhz. symbol parameter conditions min typ max unit f adc adc clock frequency 0.5 4mhz v ain conversion voltage range v ss v dd v c adc internal sample and hold capacitor 6 pf t conv conversion time flash, f adc =4mhz 28 s 112 1/f adc rom, f adc =4mhz 3.5 s 14 1/f adc r ain external input impedance see figure 97 and figure 98 1)2)3) k ? c ain external capacitor on analog input pf f ain variation frequency of analog input signal hz 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 4 mhz 2 mhz 1 mhz 0.1 1 10 100 1000 0.01 0.1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st72xxx v dd i l 1 a v t 0.6v v t 0.6v c adc 6pf v ain r ain 10-bit a/d conversion 2k ?( max ) c ain st72260gx, st72262gx, st72264gx 158/172 adc characteristics (cont?d) 13.12.0.1 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to sh ield the noise-sensitive, analog physical interface from noise generating cmos logic signals. ? properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital out- puts on the same i/o port as the a/d input being converted. adc accuracy with f cpu =8 mhz, f adc =4 mhz r ain < 10 k ?, v dd = 4.5v to 5.5v figure 100. adc accuracy characteristics notes: 1. adc accuracy vs. negative injectio n current: injecting negative current on any of the analog input pins significantly reduces the accuracy of the conver sion being performed on another analog input. for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 4 lsb for each 10k ? increase of the external analog source impedance. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive inject ion current within the limits spec- ified for i inj(pin) and i inj(pin) in section 13.8 does not affect the adc accuracy. 2. refer to ?typical values? on page 126 for more information on typical adc accuracy values. symbol parameter conditions flash rom unit typ 2) max typ 2) max |e t | total unadjusted error 1) 4 6 tbd tbd lsb | e o | offset error 1) 1 5 tbd tbd | e g | gain error 1) 1 4.5 tbd tbd |e d | differential linearity error 1) 1.5 4.5 tbd tbd |e l | integral linearity error 1) 3 4.5 tbd tbd e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss st72260gx, st72262gx, st72264gx 159/172 14 package characteristics 14.1 package mechanical data figure 101. 32-pin plastic dual in-line package, shrink 400-mil width figure 102. figure 103. 28-pin plastic small outline package, 300-mil width dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 ec 1.40 0.055 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n 32 d b2 b e a a1 a2 l e1 e ec c ea eb dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 17.70 18.10 0.697 0.713 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 28 h x 45 c l a a a1 e b d h e l st72260gx, st72262gx, st72264gx 160/172 figure 104. low profile fine pitch ball grid array package 14.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipati on determined by the user. 2. the average chip-junction temperatur e can be obtained from the formula t j = t a + p d x rthja. dim mm inches min typ max min typ max a 1.210 1.700 0.048 0.067 a1 0.270 0.011 a2 1.120 0.044 b 0.450 0.500 0.550 0.018 0.020 0.022 d 5.750 6.000 6.150 0.226 0.236 0.242 d1 4.000 0.157 e 5.750 6.000 6.150 0.226 0.236 0.242 e1 4.000 0.157 e 0.720 0.800 0.880 0.028 0.031 0.035 f 0.850 1.000 1.150 0.033 0.039 0.045 ddd 0.120 0.005 ? b (36 balls) bottom view a1 corner index area (see note 3) a a1 a2 seating plane ddd c c d d1 e f f e e1 e symbol ratings value unit r thja package thermal resistance (junction to ambient) sdip32 so28 lfbga 6x6 (on multilayer pcb) lfbga 6x6 (on single-layer pcb) 60 75 56 72 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c st72260gx, st72262gx, st72264gx 161/172 14.3 lead-free package information stmicroelectronics is fully committed to environ- ment protection and sustainable development and started in 1997 a volontary program for removing polluting and hazardous substances from all de- vices. in 2000, a strategic program, named eco- pack?, has been officially launched to develop and implement solutions leading to environment friendly packaging and ban progressively pb and other heavy metals from our manufacturing lines. please refer to application notes an2033, an2034, an2035 and an2036 for further informa- tion. st72260gx, st72262gx, st72264gx 162/172 15 device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (rom/fastrom). st7226x devices are ro m versions. st72p26x devices are factory advanced service technique rom (fastrom) versions: they are factory-pro- grammed xflash devices. st72f26x xflash devices are shipped to custom- ers with a default program memory content (ffh). the option bytes are programmed to enable the in- ternal rc oscillator. the rom/fastrom factory coded parts contain the code supplied by the cus- tomer. this implies that flash devices have to be configured by the customer using the option bytes while the rom/fastrom devices are factory- configured. 15.1 option bytes the two option bytes allow the hardware configu- ration of the microcontroller to be selected. the option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 program- ming tool). the default content of the flash is fixed to ffh. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). user option byte 0 opt 7 = wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt 6 = wdg sw hardware or software watch- dog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt 5:4 = vd[1:0] voltage detection selection these option bits enable the voltage detection block (lvd and avd) with a selected threshold of the lvd and avd. opt 3:2 = sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 ac- cording to the following table. note 1: 4k available on fastrom devices only. opt 1 = fmp_r read-out protection read-out protection, when selected, provides a protection against program memory content ex- traction and against write access to flash memo- ry. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first, and the device can be reprogrammed. refer to section 4.5 and the st7 flash program- ming reference manual for more details. 0: read-out protection off 1: read-out protection on configuration vd1 vd0 lvd off 11 lowest voltage threshold ( 3.05v) 1 0 medium voltage threshold ( 3.6v) 01 highest voltage threshold ( 4.1v) 00 sector 0 size sec1 sec0 0.5k 00 1k 01 2 10 4k 1) 11 user option byte 0 70 user option byte 1 70 wdg halt wdg sw vd1 vd0 sec 1 sec 0 fmp r fmp w extit res. osc type 1 osc type 0 osc rnge 2 osc rnge 1 osc rnge 0 pll off default value 11111100 1 1 1 0 1 1 1 1 1 st72260gx, st72262gx, st72264gx 163/172 device configuration (cont?d) opt 0 = fmp_w flash write protection this option indicates if the flash program mem- ory is write protected. warning: when this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: write protection off 1: write protection on user option byte 1 opt 7 = extit port c external interrupt configu- ration . this option bit allows the port c external interrupt mapping to be configured as ei0 or ei1. table 27. external interrupt configuration opt 6 = reserved, must be kept at default value. opt 5:4 = osctype[1:0] oscillator type selec- tion these option bits select the oscillator type. opt 3:1 = oscrnge[2:0] oscillator range se- lection these option bits select the oscillator range. opt 0 = pll pll selection this option bit selects th e pll which allows multi- plication by two of the oscillator frequency. the pll must not be used with the internal rc oscilla- tor. it is guaranteed only with a f osc input frequen- cy between 2 and 4mhz. 0: pll x2 enabled 1: pll x2 disabled caution : the pll can be enabled only if the ?osc range? (opt3:1) bits are configured to ?mp - 2~4mhz?. otherwise, the device functionali- ty is not guaranteed. ei0 ei1 extit option bit pa[7:0] ports pb[7:0] ports pc[5:0] ports 1 pa[7:0] ports pc[5:0] ports pb[7:0] ports 0 clock source osctype1 osctype0 resonator oscillator 0 0 reserved 0 1 internal rc oscillator 1 0 external source 1 1 typ. freq. range osc rnge2 osc rnge1 osc rnge0 vlp 32~100khz 1 x x lp 1~2mhz 0 0 0 mp 2~4mhz 0 0 1 ms 4~8mhz 0 1 0 hs 8~16mhz 0 1 1 1 st72260gx, st72262gx, st72264gx 164/172 15.2 device ordering informat ion and transfer of customer code customer code is made up of the rom/fas- trom contents and the list of the selected options (if any). the rom/fastrom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the develop- ment tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 28. supported part numbers part number program memory (bytes) ram (bytes) temp. range package st72f264g1b6 4k flash 256 -40c +85c sdip32 st72f264g1m6 so28 st72f262g1b6 sdip32 st72f262g1m6 so28 st72f264g2b6 8k flash 256 sdip32 st72f264g2m6 so28 st72f264g2h1 0c +70c lfbga st72f264g2h6e -40c +85c lead-free lfbga st72f262g2b6 -40c +85c sdip32 st72f262g2m6 so28 st72f262g1b6 4k flash 256 sdip32 st72f262g1m6 so28 st72f260g1b6 sdip32 st72f260g1m6 so28 st72p264g2b6/xxx 8k fastrom 256 -40c +85c sdip32 st72p264g2m6/xxx so28 st72p264g2h1/xxx 0c +70c lfbga st72p262g2b6/xxx -40c +85c sdip32 st72p262g2m6/xxx so28 st72p262g1b6/xxx 4k fastrom 256 sdip32 st72p262g1m6/xxx so28 st72p260g1b6/xxx sdip32 st72p260g1m6/xxx so28 st72264g2b6/xxx 8k rom 256 -40c +85c sdip32 st72264g2m6/xxx so28 st72262g2b6/xxx sdip32 st72262g2m6/xxx so28 st72262g1b6/xxx 4k rom 256 sdip32 st72262g1m6/xxx so28 st72260g1b6/xxx sdip32 st72260g1m6/xxx so28 1 st72260gx, st72262gx, st72264gx 165/172 transfer of customer code (cont?d) st72264 rom/fastrom microc ontroller option list (last update: 15 january 2004) customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference /rom or fastrom code* rom or fastrom code is as signed by stmicroelectronics. code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option): conditioning (check only one option , do not specify for dip package): so package: [ ] tape & reel [ ] tube die form: [ ] tape & reel [ ] inked wafer [ ] sawn wafer on sticky foil special marking [ ] no [ ] yes authorized characters are letters, di gits ?.?, ?-?, ?/? and spaces only. maximum character count: so28 (13 char. max): _ _ _ _ _ _ _ _ _ _ _ _ _ sdip32 (15 char. max): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ bga6x6 (7 char. max): _ _ _ _ _ _ _ temperature range: packaged form: [ ] 0c to + 70c [ ] - 10c to + 85c (except bga) [ ] - 40c to + 85c (except bga) die form: [ ] tested at 25c only watchdog reset on halt: [ ] reset [ ] no reset watchdog selection: [ ] software activation [ ] hardware activation vd reset [ ] disabled [ ] enabled: [ ] highest threshold [ ] medium threshold [ ] lowest threshold sector 0 size: [ ] 0.5k [ ] 1k [ ] 2k [ ] 4k (fastrom only) readout protection: [ ] disabled [ ] enabled flash write protection: [ ] dis abled [ ] enabled (fastrom only) external interrupt: [ ] port a&c on ei0 interrupt vector, port b on ei1 (pa&c_pb) [ ] port a on ei0 interrupt vector, port b&c on ei1 (pa_pb&c) clock source selection: [ ] resonator: [ ] vlp: very low power resonator (32 to 100 khz) [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] internal rc oscillator 1) [ ] external clock pll 1 : [ ] disabled [ ] enabled supply operating range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 1: use of the pll with the in ternal rc oscillator is not supported. important note: not all configurations are available. see table 28 on page 164 for the list of supported part numbers. please download the latest versi on of this option list from: http://www.st.com/mcu > downloads > st7 microcontrollers > option list ---------------------------- rom device: ---------------------------- | | -------------------------------------------- 8k -------------------------------------------- | | ---------------------------------------------------------------- 4k ---------------------------------------------------------------- so28: | [ ]st72264g2 [ ]st72262g2 | [ ]st72264g1 [ ]st72262g1 [ ]st72260g1 sdip32: | [ ]st72264g2 [ ]st72262g2 | [ ]st72264g1 [ ]st72262g1 [ ]st72260g1 --------------------------- fastrom device: ---------------------------- | | -------------------------------------------- 8k -------------------------------------------- | | ---------------------------------------------------------------- 4k ---------------------------------------------------------------- so28: | [ ]st72p264g2 [ ]st72p262g2 | [ ]st72p264g1 [ ]st72p262g1 [ ]st72p260g1 sdip32: | [ ]st72p264g2 [ ]st72p262g2 | [ ]st72p264g1 [ ]st72p262g1 [ ]st72p260g1 bga6x6: | [ ]st72p264g2 | ---------------------------- die form: ---------------------------- | | ------------------------------------------- [ ] 8k -------------------------------------------- | | ---------------------------------------------------------------- [ ] 4k ---------------------------------------------------------------- st72260gx, st72262gx, st72264gx 166/172 15.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tained from the stmicroelectronics internet site: http//www.st.com. tools from these manufacturers include c compli- ers, evaluation tools, emulators and programmers. emulators two types of emulators are available from st for the st72260/262/264 family: st7 dvp3 entry-level emulator offers a flexible and modular debugging and programming solution. st7 emu3 high-end emulator is delivered with everything (probes, teb, adapters etc.) needed to start emulating the st72260/262/264. to configure it to emulate other st7 subfamily devices, the active probe for the st7emu3 can be changed and the st7emu3 probe is designed for easy interchange of tebs (target emulation board). see table 29 . in-circuit debugging kit three configurations are available from st: st7f264-ind/usb: low-cost in-circuit debugging kit from so ftec microsystems. includes stx-indart/usb board (usb port) and one specific evaluation board for st72264 (package sdip32) st7f264-indart: lo w-cost in-circuit debugging kit from softec microsystems includes stx-indart/usb board (parallel port) and one specific evaluation board for st72264 (package sdip32) stxf-indart/usb flash programming tools st7-stick st7 in-circuit communication kit, a complete software/hardware package for programming st7 flash devices. it connects to a host pc parallel port and to the target board or socket board via st7 icc connector. icc socket boards provide an easy to use and flexible means of programming st7 flash devices. they can be connected to any tool that supports the st7 icc interface, such as st7 emu3, st7-dvp3, indart, st7-stick, or many third-party development tools. evaluation boards one evaluation tool is available from st: st7foptions-eval: st7 clock security system evaluation board table 29. stmicroelectronics development tools notes : 1. bga adapter not available for st7mdt10-dvp3 and st7mdt10-emu3 . 2. add suffix /eu, /uk, /us for the power supply of your region. 15.3.1 related documentation an 978: key features of the stvd7 st7 visual debug package an 983: key features of the cosmic st7 c-com- piler package an 988: getting started with st7 assembly tool chain an 989: getting started with st7 hiware c tool- chain an1604: how to use st7mdt1-train with st72f264 supported products emulation programming st7 dvp3 series st7 emu3 series icc socket board emulator connection kit emulator active probe & t.e.b. st7226xgx st7mdt10- dvp3 1) st7mdt10-32/dvp st7mdt10- emu3 1) st7mdt10-teb st7sb10-26x 2) 1 st72260gx, st72262gx, st72264gx 167/172 15.3.2 package/socket footprint proposal table 30. suggested list of sdip32 socket types table 31. suggested list of so28 socket types table 32. suggested lfbga socket type package / probe adaptor / socket reference same footprint socket type sdip32 emu probe textool 232-1291-00 x textool package / probe adaptor / socket reference same footprint socket type so28 yamaichi ic51-0282-334-1 clamshell emu probe adapter from so28 to sdip32 footpr int (delivered with emulator) x smd to sdip package socket reference lfbga 6 x6 enplas otb-36(144)-0.8-04 1 st72260gx, st72262gx, st72264gx 168/172 16 known limitations 16.1 all flash and rom devices 16.1.1 16-bit timer pwm mode in pwm mode, the first pwm pulse is missed after writing the value fffch in the oc12r register.in pwm mode, the first pwm pulse is missed after writing the value fffch in the oc1r register (oc1hr, oc1lr). it leads to either full or no pwm during a period, depending on the olvl1 and olvl2 settings. 16.1.2 clearing active interrupts outside interrupt routine when an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the cc register may be corrupted. concurrent interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: ? the interrupt request is cleared (flag reset or in- terrupt mask) within its own interrupt routine ? the interrupt request is cleared (flag reset or in- terrupt mask) within any interrupt routine ? the interrupt request is cleared (flag reset or in- terrupt mask) in any part of the code while this in- terrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following se- quence: perform sim and rim operation before and after resetting an active interrupt request ex: sim reset flag or interrupt mask rim nested interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: ? the interrupt request is cleared (flag reset or in- terrupt mask) within its own interrupt routine ? the interrupt request is cleared (flag reset or in- terrupt mask) within any interrupt routine with higher or identical priority level ? the interrupt request is cleared (flag reset or in- terrupt mask) in any part of the code while this in- terrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following se- quence: push cc sim reset flag or interrupt mask pop cc 16.1.3 i2c multimaster in multimaster configurat ions, if the st7 i2c re- ceives a start condition from another i2c mas- ter after the start bit is set in the i2ccr register and before the start condition is generated by the st7 i2c, it may ignore the start condition from the other i2c master. in this case, the st7 master will receive a nack from the other device. on reception of the nack, st7 can send a re-start and slave address to re-initiate communication 16.1.4 functional ems the functional ems (electro magnetic susceptibil- ity) severity level/behaviour class is 2b as defined in application note an1709. special care should be taken when designing the pcb layout and firmware (refer to application notes an898, an901 and an1015) in sensitive applications (that use switches for instance). for more information refer to application note an1637. 16.2 flash devices only 16.2.1 execution of btjx instruction when testing the address $ff with the "btjt" or "btjf" instructions, the cpu may perform an in- correct operation when the relative jump is nega- tive and performs an address page change. to avoid this issue, including when using a c com- piler, it is recommended to never use address $00ff as a variable (using the linker parameter for example). 1 st72260gx, st72262gx, st72264gx 169/172 16.2.2 i/o port b and c configuration when using an external quartz crystal or ceramic resonator, the f osc2 clock may be disturbed be- cause the device goes into reserved mode control- led by port b and c. this happens with either one of the following con- figurations: pb1=0, pc2=1, pb3=0 while pll option is both disabled and pc4 is toggling pb1=0, pc2=1, pb3=0, pc4=1 while pll option is enabled this is detailed in the following table: as a consequence, for cycle-accurate operations, these configurations are prohibited in either input or output mode. workaround: to avoid this occurring, it is recommended to con- nect one of these pins to gnd (pc2 or pc4) or v dd (pb1 or pb3). 16.2.3 16-bit timer pwm mode after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 16.2.4 spi multimaster mode multi master mode is not supported. 16.2.5 internal rc oscillator with lvd if the lvd is disabled, th e internal rc oscillator clock source cannot be used. in icp mode, new flash devices must be pro- grammed with an external clock connected to the osc1 pin or using a crystal or ceramic resonator. in the stvp7 programming tool software, select the ?options disabled? mode. 16.2.6 external clock with pll the pll option is not supported for use with exter- nal clock source. 16.2.7 halt mode power consumption with adc on if the a/d converter is being used when halt mode is entered, the power consumption in halt mode may exceed the maximum specified in the datash- eet. workaround switch off the adc by software (adon=0) before executing a halt instruction. 16.2.8 active halt wake-up by external interrupt external interrupts are not able to wake-up the mcu from active halt mode. the mcu can only exit from active halt mode by means of an mcc/ rtc interrupt or a reset. workaround use wait mode if extern al interrupt capability is required in low power mode. 16.2.9 sci wrong break duration description a single break character is sent by setting and re- setting the sbk bit in the scicr2 register. in some cases, the break ch aracter may have a long- er duration than expected: - 20 bits instead of 10 bits if m=0 - 22 bits instead of 11 bits if m=1. in the same way, as long as the sbk bit is set, break characters are sent to the tdo pin. this may lead to generate one break more than expect- ed. occurrence the occurrence of the problem is random and pro- portional to the baudrate. with a transmit frequen- cy of 19200 baud (fcpu=8mhz and sci- brr=0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with the communication protocol in the application, soft- ware can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the applica- tion is not doing anything between the idle and the break. this can be ensured by temporarily disa- bling interrupts. the exact sequence is: ? disable interrupts ? reset and set te (idle request) ? set and reset sbk (break request) ? re-enable interrupts 16.2.10 a/d converter accuracy for first conversion when the adc is enabled after being powered down (for example when waking up from halt, active-halt or setting the adon bit in the ad- ccsr register), the first conversion (8-bit or 10- pll pb1 pc2 pb3 pc4 clock disturbance off 0 1 0 tog glin g max. 2 clock cycles lost at each rising or falling edge of pc4 on0101 max. 1 clock cycle lost out of every 16 st72260gx, st72262gx, st72264gx 170/172 bit) accuracy does not meet the accuracy specified in the data sheet. workaround in order to have the accuracy specified in the da- tasheet, the first conversion after a adc switch-on has to be ignored. 16.2.11 negative injection impact on adc accuracy injecting a negative current on an analog input pins significantly reduces the accuracy of the ad converter. whenever necessary, the negative in- jection should be prevented by the addition of a schottky diode between the concerned i/os and ground. injecting a negative current on digital input pins degrades adc accuracy especially if performed on a pin close to adc channel in use. 16.2.12 adc conversion spurious results spurious conversions occur with a rate lower than 50 per million. such conv ersions happen when the measured voltage is just between 2 consecutive digital values. workaround a software filter should be implemented to remove erratic conversion results whenever they may cause unwanted consequences. st72260gx, st72262gx, st72264gx 171/172 17 revision history table 33. revision history date rev. main changes february-2005 2.0 added ?smbus v1.1 compliant? for i2c on page 1 added one note in section 6.4.1 on page 24 added smbus compatibility information in section 11.6 on page 103 and at the end of section 11.6.4.1 on page 105 changed note 1 in section 13.2 on page 127 added note 3 in section 13.3.2 on page 129 changed i s value and note 3 in section 13.8.1 on page 144 added note in figure 76 on page 144 changed figure 91 on page 151 and notes and added note 4 to figure 92 on page 151 added ?lead-free package information? on page 161 added st72f264g2h6e in table 28, ?supported part numbers,? on page 164 changed section 15.3 on page 166 changed ?st72264 rom/fastrom microcontroller option list (last update: 15 january 2004)? on page 165 01-jun-05 3 added -40c to +85c operating range in ?dev ice summary? on first page for lfbga package (lead-free lfbga package) added illegal opcode reset on page 1, and in section 12.2.1 on page 123 changed notes under figure 91 on page 151 changed vt por max. for rom and note 3. removed v hys min and maxin section 13.3.2 on page 129 changed reset v il /v ih in section 13.9 on page 150 added rom current consumption in section 13.4.1 on page 131 added active halt min.in section 13.4.2 on page 133 removed note under table in section 13.7.2 on page 142 changed note on pb0/pb1 to apply to flash only in section 13.2 on page 127 and section 13.8 on page 144 added v dd range for adc operation, f adc min , conversion time and accuracy for rom devices in section 13.12 on page 157 . added 16-bit timer pwm section 16.2.3 on page 169 added sci wrong break duration section 16.2.9 on page 169 moved errata sheet to section 16 on page 168 and updated section for rom and flash devices st72260gx, st72262gx, st72264gx 172/172 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - 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